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KR-20260067004-A - SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

KR20260067004AKR 20260067004 AKR20260067004 AKR 20260067004AKR-20260067004-A

Abstract

A semiconductor device may include a first laminate comprising first insulating films and second insulating films that are alternately stacked; a through structure extending through the first laminate and including an air gap; and a second laminate located below the first laminate and including a key pattern located corresponding to the air gap.

Inventors

  • 김종훈

Assignees

  • 에스케이하이닉스 주식회사

Dates

Publication Date
20260512
Application Date
20241105

Claims (20)

  1. A first laminate comprising first insulating films and second insulating films alternately stacked; A through-structure extending through the first laminate and including an air gap; and A second laminate located at the bottom of the first laminate and including a key pattern located corresponding to the air gap A semiconductor device including
  2. In paragraph 1, The above penetration structure is, Insulating liner; and The air gap located inside the insulation liner Semiconductor device.
  3. In paragraph 2, A metal pattern located on the upper part of the first laminate; and An interlayer insulating film located between the first laminate and the metal pattern A semiconductor device further comprising
  4. In paragraph 3, The above insulating liner and the above interlayer insulating film are a single film integrally connected. Semiconductor device.
  5. In paragraph 3, A conductive pattern located between the first laminate and the interlayer insulating film A semiconductor device further comprising
  6. In paragraph 5, The above challenge pattern comprises polysilicon. Semiconductor device.
  7. In paragraph 1, The above penetration structure is, Metal liner; An insulating liner wrapping the metal liner above; and The air gap located inside the metal liner Semiconductor device.
  8. In Paragraph 7, The metal liner above protrudes from the upper surface of the first laminate. Semiconductor device.
  9. In paragraph 1, The second laminate comprises alternately stacked third material films and fourth material films, and includes the key pattern on its upper surface. Semiconductor device.
  10. In Paragraph 9, The third insulating films and the fourth insulating films are laminated in a recessed form toward the through structure, and the key pattern includes a groove located in the recessed area. Semiconductor device.
  11. In paragraph 1, The above through-hole structure has an upper width that is narrower than its lower width. Semiconductor device.
  12. In paragraph 1, The above penetration structure is located in the scribe area Semiconductor device.
  13. In paragraph 1, A memory cell array comprising a gate structure located at a level corresponding to the first stack and the second stack; Peripheral circuits; A bonding structure that electrically connects the memory cell array and the peripheral circuit. A semiconductor device further comprising
  14. In paragraph 1, A gate structure located at a level corresponding to the first stack and the second stack; A source film located on the upper part of the gate structure; and Metal wiring located on the upper part of the above source membrane A semiconductor device further comprising
  15. In Paragraph 14, A metal pattern located on the upper part of the first laminate and at a level corresponding to the metal wiring. A semiconductor device further comprising
  16. A laminate comprising first insulating films and second insulating films alternately stacked and located in a scribe line area; A metal liner extending vertically through the above laminate; An insulating liner wrapping the above metal liner; An air gap located inside the metal liner; and An interlayer insulating film located on the upper part of the above laminate A semiconductor device including
  17. In Paragraph 16, A conductive pattern located between the first laminate and the interlayer insulating film A semiconductor device further comprising
  18. In Paragraph 16, A metal pattern located on the upper side of the interlayer insulating film and in contact with the air gap or the metal liner. A semiconductor device further comprising
  19. In Paragraph 16, The above insulating liner and the above interlayer insulating film are a single film integrally connected. Semiconductor device.
  20. Step of forming a first laminate on a substrate; A step of forming a first opening extending into the substrate through the first laminate; A step of forming a sacrificial membrane within the first opening; A step of forming a second laminate on the first laminate; A step of etching the substrate so as to expose the sacrificial film; A step of removing the sacrificial membrane to form a second opening; and Step of forming an air gap within the second opening A method for manufacturing a semiconductor device including

Description

Semiconductor Device and Manufacturing Method of Semiconductor Device The present invention relates to an electronic device, and more specifically to a semiconductor device and a method for manufacturing a semiconductor device. The integration density of a semiconductor device is primarily determined by the area occupied by a unit memory cell. Recently, as the improvement of integration density in semiconductor devices that form memory cells as a single layer on a substrate has reached its limit, three-dimensional semiconductor devices that stack memory cells on a substrate are being proposed. In addition, various structures and manufacturing methods are being developed to improve the operational reliability of such semiconductor devices. FIGS. 1a to 1e are drawings showing the structure of a semiconductor device according to one embodiment of the present invention. FIGS. 2A and FIGS. 2B are drawings showing the structure of a semiconductor device according to one embodiment of the present invention. FIGS. 3a and FIGS. 3b are drawings showing the structure of a semiconductor device according to one embodiment of the present invention. FIGS. 4a to 4e are drawings for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIGS. 5a to 5c are drawings for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIGS. 6a to 17a and FIGS. 6b to 17b are drawings for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 18 is a configuration diagram of a semiconductor device according to one embodiment of the present invention. FIG. 19 is a configuration diagram of a semiconductor device according to one embodiment of the present invention. Hereinafter, embodiments according to the technical concept of the present invention will be described with reference to the attached drawings. FIGS. 1a to 1e are drawings showing the structure of a semiconductor device according to one embodiment of the present invention. Referring to FIGS. 1a through 1e, the semiconductor device may include a first stack (ST1), a second stack (ST2), a through-structure (PS), and a metal pattern (15). The semiconductor device may further include a conductive pattern (19) and an interlayer insulating film (16). For reference, the number of stacks included in the semiconductor device may be changed. The semiconductor device may not include the second stack (ST2) or may further include a third stack (ST3). The first stack (ST1) may include first material films (11) and second material films (12) that are alternately stacked. The first material films (11) may include a material with a high etching selectivity ratio with respect to the second material films (12). As an example, the first material films (11) may include a nitride and the second material films (12) may include an oxide. The first material films (11) may include a conductive material and the second material films (12) may include an insulating material. The through structure (PS) may be located within the first laminate (ST1). The through structure (PS) may extend through the first laminate (ST1) and may extend in a vertical direction. The through structure (PS) may have a tapered cross-section and may have a narrower upper width compared to its lower width. The through structure (PS) may include an air gap (AG). The air gap (AG) may be an empty space not filled with a material film. The second layer (ST2) may be located below the first layer (ST1). The second layer (ST2) may include alternately stacked third material films (13) and fourth material films (14). As an example, the third material films (13) may include nitrides and the fourth material films (14) may include oxides. The third material films (13) may include conductive materials and the fourth material films (14) may include insulating materials. The third material films (13) may include the same material as the first material films (11), and the fourth material films (14) may include the same material as the second material films (12). A through-structure (PS) may be positioned on the upper part of the second laminate (ST2), and the second laminate (ST2) may include a key pattern (K) positioned corresponding to the through-structure (PS). The key pattern (K) may be positioned on the surface of the second laminate (ST2) and may be a pattern formed by the stacking shape of the third and fourth material films (13, 14). The third and fourth material films (13, 14) may be stacked in a recessed shape toward the through-structure (PS), and the groove of the recessed area may be the key pattern (K). A conductive pattern (19) may be located on top of the first laminate (ST1). An interlayer insulating film (16) may be located on top of the conductive pattern (19). A metal pattern (15) may be located on top of the interlayer insulating film (16). An interl