KR-20260067139-A - Semiconductor package

Abstract

A semiconductor package capable of improving device performance and reliability is provided. The semiconductor package comprises a first semiconductor die including a first surface and a second surface opposite in a vertical direction, and a second semiconductor die including a third surface and a fourth surface opposite in a vertical direction, wherein the third surface of the second semiconductor die faces the second surface of the first semiconductor die, a first bonding layer in contact with the first surface of the first semiconductor die, and a second bonding layer disposed between the second surface of the first semiconductor die and the third surface of the second semiconductor die and in contact with the second surface of the first semiconductor die, wherein the width of the first bonding layer in the horizontal direction is smaller than the width of the second bonding layer in the horizontal direction, and the width of the second bonding layer in the horizontal direction is larger than the width of the first semiconductor die in the horizontal direction.

Inventors

• 장주희
• 이호진
• 민준홍
• 손성민
• 이승돈
• 이현진
• 임동찬

Assignees

• 삼성전자주식회사

Dates

Publication Date

20260512

Application Date

20241105

Claims (10)

1. A first semiconductor die comprising a first surface and a second surface opposite in the vertical direction; A second semiconductor die comprising a third surface and a fourth surface opposite in the vertical direction, wherein the third surface of the second semiconductor die faces the second surface of the first semiconductor die; A first bonding layer in contact with a first surface of the first semiconductor die; and It includes a second bonding layer disposed between the second surface of the first semiconductor die and the third surface of the second semiconductor die, and in contact with the second surface of the first semiconductor die. The width of the first bonding layer in the horizontal direction is smaller than the width of the second bonding layer in the horizontal direction, and A semiconductor package in which the width of the second bonding layer in the horizontal direction is greater than the width of the first semiconductor die in the horizontal direction.
2. In Article 1, A semiconductor package in which the width of the first bonding layer in the horizontal direction is the same as the width of the first semiconductor die in the horizontal direction.
3. In Article 1, A semiconductor package further comprising a filling film that covers the sidewall of the first semiconductor die and contacts the second bonding layer.
4. In Article 1, A third bonding layer in contact with the third surface of the second semiconductor die and the second bonding layer, and It further includes a fourth bonding layer in contact with the fourth surface of the second semiconductor die, and A semiconductor package in which the width of the third bonding layer in the horizontal direction is different from the width of the fourth bonding layer in the horizontal direction.
5. In Paragraph 4, A first filling film covering the sidewall of the first semiconductor die and in contact with the second bonding layer; and A semiconductor package further comprising a second filling film that covers the sidewall of the second semiconductor die and contacts the third bonding layer.
6. In Paragraph 4, A semiconductor package in which the width of the third bonding layer in the horizontal direction is greater than the width of the fourth bonding layer in the horizontal direction.
7. A first semiconductor die comprising a first surface and a second surface opposite in the vertical direction; A second semiconductor die comprising a third surface and a fourth surface opposite in the vertical direction, wherein the third surface of the second semiconductor die faces the second surface of the first semiconductor die; A first bonding layer in contact with a first surface of the first semiconductor die; and It includes a second bonding layer disposed between the second surface of the first semiconductor die and the third surface of the second semiconductor die, and in contact with the second surface of the first semiconductor die. The width of the first bonding layer in the horizontal direction is greater than the width of the second bonding layer in the horizontal direction, and A semiconductor package in which the width of the second bonding layer in the horizontal direction is the same as the width of the first semiconductor die in the horizontal direction.
8. In Article 7, A third bonding layer in contact with the third surface of the second semiconductor die and the second bonding layer; A fourth bonding layer in contact with the fourth surface of the second semiconductor die; A first bonding pad disposed on a first surface of the first semiconductor die and penetrating the first bonding layer; A second bonding pad disposed on a second surface of the first semiconductor die and penetrating the second bonding layer; A third bonding pad disposed on a third surface of the second semiconductor die and penetrating the third bonding layer; and It further includes a fourth bonding pad disposed on the fourth surface of the second semiconductor die and penetrating the fourth bonding layer, and The semiconductor package in which the second bonding pad and the third bonding pad are in direct contact.
9. In Article 7, A first via disposed between the first bonding pad and the second bonding pad and connecting the first bonding pad and the second bonding pad; and A semiconductor package further comprising a second via disposed between the third bonding pad and the fourth bonding pad, and connecting the third bonding pad and the fourth bonding pad.
10. Base substrate; A first semiconductor die disposed on the base substrate and comprising a first surface and a second surface opposite in the vertical direction; A second semiconductor die comprising a third surface and a fourth surface opposite in the vertical direction, wherein the third surface of the second semiconductor die faces the second surface of the first semiconductor die; A first bonding layer in contact with a first surface of the first semiconductor die; A second bonding layer disposed between the second surface of the first semiconductor die and the third surface of the second semiconductor die, and in contact with the second surface of the first semiconductor die; A third bonding layer in contact with the third surface of the second semiconductor die and the second bonding layer; A fourth bonding layer in contact with the fourth surface of the second semiconductor die; and It includes a filling film that covers the sidewalls of the first semiconductor die and the second semiconductor die and contacts the first bonding layer and the fourth bonding layer, The width of the first bonding layer in the horizontal direction is greater than the width of the second bonding layer in the horizontal direction, and A semiconductor package in which the width of the second bonding layer in the horizontal direction is the same as the width of the first semiconductor die in the horizontal direction.

Description

Semiconductor package The present invention relates to a semiconductor package. Many modern electronic devices use integrated chips formed on semiconductor wafers during the semiconductor device manufacturing process. Increasingly, semiconductor wafers can be stacked and bonded together to form multidimensional integrated chips. Multidimensional integrated chips have many advantages over conventional two-dimensional integrated chips, such as higher device density, faster speeds, and lower power consumption. FIG. 1 is a drawing for illustrating a semiconductor package according to some embodiments of the present invention. FIG. 2 is an enlarged view of area A of FIG. 1 to illustrate a semiconductor package according to some embodiments of the present invention. FIG. 3 is a schematic perspective view showing the first semiconductor die, the first bonding layer, and the second bonding layer of FIG. 1 to illustrate a semiconductor package according to some embodiments of the present invention. FIGS. 4 to 22 are intermediate step drawings for explaining a semiconductor package manufacturing method according to some embodiments of the present invention. Embodiments of the present invention will be described in detail below with reference to the attached drawings. Identical components in the drawings are denoted by the same reference numerals, and redundant descriptions thereof are omitted. In this specification, although terms such as "first," "second," etc. are used to describe various elements or components, it is understood that these elements or components are not limited by these terms. These terms are used merely to distinguish one element or component from another. Therefore, it is understood that the first element or component mentioned below may be the second element or component within the technical scope of the present invention. FIG. 1 is a drawing for illustrating a semiconductor package according to some embodiments of the present invention. FIG. 2 is an enlarged view of area A of FIG. 1 for illustrating a semiconductor package according to some embodiments of the present invention. FIG. 3 is a schematic perspective view showing the first semiconductor die, the first bonding layer, and the second bonding layer of FIG. 1 for illustrating a semiconductor package according to some embodiments of the present invention. Referring to FIGS. 1 to 3, a semiconductor package according to some embodiments of the present invention may include a base substrate (300), a first semiconductor die (101), a second semiconductor die (102), a third semiconductor die (103), a fourth semiconductor die, a fifth semiconductor die (105), a sixth semiconductor die (106), a first filling film (501), a second filling film (502), a third filling film (503), a fourth filling film (504), a fifth filling film (505), and a sixth filling film (506). The base substrate (300) may be a semiconductor substrate. The base substrate (300) may include an internal circuit. Specifically, the base substrate (300) may include electronic components such as transistors. However, as another example, the base substrate (300) may be a substrate that does not include electronic components such as transistors, for example, a printed circuit board (PCB). The first to sixth semiconductor dies (101, 102, 103, 104, 105, 106) may be memory chips or logic chips. For example, the first to sixth semiconductor dies (101, 102, 103, 104, 105, 106) may all be the same type of memory chip. As another example, some of the first to sixth semiconductor dies (101, 102, 103, 104, 105, 106) may be memory chips and others may be logic chips. In some embodiments, the first to sixth semiconductor dies (101, 102, 103, 104, 105, 106) may be High Bandwidth Memory (HBM) chips. Although only the first semiconductor die (101) is described below, the second to sixth semiconductor dies (102, 103, 104, 105, 106) may also include the same structure. A fourth semiconductor die (104), a third semiconductor die (103), a first semiconductor die (101), a second semiconductor die (102), a fifth semiconductor die (105), and a sixth semiconductor die (106) can be sequentially stacked on a base substrate (300). The first semiconductor die (101) may include a first substrate (171), a first bonding pad (131), a second bonding pad (132), a first through-via (111), and a first device layer (181). A first semiconductor die (101) may be positioned between a third semiconductor die (103) and a second semiconductor die (102). The first semiconductor die (101) may include a lower surface (101BS) and an upper surface (101US) that are opposite each other in a third direction (DR3). The lower surface (101BS) of the first semiconductor die (101) may be positioned to face the third semiconductor die (103), and the upper surface (101US) may be positioned to face the second semiconductor die (102). For reference, in this specification, the first direction (DR1) and the second direction (DR2) may intersect ea