KR-20260067145-A - Semiconductor memory device and Operating methods of the semiconductor memory device

KR20260067145AKR 20260067145 AKR20260067145 AKR 20260067145AKR-20260067145-A

Abstract

A capacitorless semiconductor memory device and a method for operating a capacitorless semiconductor memory device are disclosed. The disclosed capacitorless semiconductor memory device may include a memory cell array comprising a plurality of memory cells each comprising two transistors, a sensing amplifier and a clamping circuit connected to a bit line of the memory cell array; and a control unit that controls the sensing amplifier, the clamping circuit, and the memory cell array differently according to a first mode or a second mode. The disclosed method for operating a memory cell array comprising a plurality of memory cells each comprising two transistors comprises the step of the memory cell array being connected to the sensing amplifier and the clamping circuit via a bit line, and the control unit selecting a first mode or a second mode according to a memory cell selected to read data among the memory cell array; The method includes the step of reading data from the memory cell using at least one of the operating voltage value ( Vdd ) provided by the sensing amplifier and the clamping voltage value ( Vcl ) provided by the clamping circuit according to the selected first mode or second mode, wherein the clamping voltage value may be set to a value greater than a predetermined value ( δVth ) than the difference between the operating voltage value ( Vdd ) and the threshold voltage value ( Vth ) of the memory cell.

Inventors

황철성

Assignees

서울대학교산학협력단

Dates

Publication Date: 20260512
Application Date: 20241105

Claims (13)

As a capacitorless semiconductor memory device, A memory cell array comprising a plurality of memory cells, each containing two transistors; A sensing amplifier and a clamping circuit connected to the bit lines of the memory cell array; and A control unit that controls the sensing amplifier, the clamping circuit, and the memory cell array differently according to a first mode or a second mode. Capacitorless including Semiconductor memory device.
In Article 1, A capacitorless semiconductor memory device characterized by the clamping circuit applying a clamping voltage value ( Vcl ), which is greater than a predetermined value ( δVth ) than the difference between the operating voltage value ( Vdd ) of the bit line and the threshold voltage value ( Vth ) of the memory cell, to the memory cell of the bit line according to the first mode or the second mode.
In Article 2, A capacitorless semiconductor memory device characterized by the above-described control unit selecting at least one of a plurality of read word lines included in the memory cell array in the first mode and reading data of a plurality of memory cells connected to the selected read word line.
In Paragraph 3, A capacitorless semiconductor memory device characterized by the above-described control unit controlling a sensing amplifier connected to a bit line of the memory cell array in the first mode to set the voltage of the bit line to an operating voltage value ( Vdd ) and changing the voltage of the selected read word line to 0V to read data of a plurality of memory cells connected to the selected word line.
In Article 4, In the first mode above, the clamping circuit is a capacitorless semiconductor memory device such that the minimum value of the voltage of the bit line becomes the clamping voltage value.
In Article 2, A capacitorless semiconductor memory device characterized by the above-described control unit selecting at least one of the plurality of memory cells in the second mode, controlling that an operating voltage value ( Vdd ) be applied to a bit line connected to the selected memory cell and that the clamping voltage value ( Vcl ) of the clamping circuit be applied to a bit line of the unselected memory cell to read the data of the selected memory cell.
In Article 6, A capacitorless semiconductor memory device characterized by, in the second mode above, changing the voltage of the selected word line to 0V and applying an operating voltage value ( Vdd ) to the unselected word line.
In Article 7, A semiconductor memory device characterized in that the voltage drop of the unselected memory cell does not exceed the threshold voltage value by the clamping voltage value.
A method for driving a memory cell array comprising a plurality of memory cells each comprising two transistors, The above memory cell array is connected to a sensing amplifier and a clamping circuit via a bit line, and the control unit selects a first mode or a second mode according to a memory cell selected to read data among the memory cell array; and The method includes the step of reading data from the memory cell using at least one of the operating voltage value ( Vdd ) provided by the sensing amplifier and the clamping voltage value ( Vcl ) provided by the clamping circuit according to the selected first mode or second mode, The above clamping voltage value is set to a value ( δVth ) greater than the difference between the above operating voltage value ( Vdd ) and the threshold voltage value ( Vth ) of the memory cell, in a capacitorless manner. Driving method of a semiconductor memory device.
In Article 9, The step of reading data from the memory cell above is, A method for driving a capacitorless semiconductor memory device, characterized by the step of, when the first mode is selected, controlling a sensing amplifier connected to the bit line of the memory cell to read the data to set the voltage of the bit line to an operating voltage value ( Vdd ), changing the word line voltage of the memory cell to read the data to 0V, and reading the data of a plurality of memory cells connected to the selected word line.
In Article 10, The above clamping circuit is a driving method for a capacitorless semiconductor memory device such that the minimum value of the voltage of the bit line in the first mode becomes the clamping voltage value.
In Article 9, The step of reading data from the memory cell above is, A method for driving a capacitorless semiconductor memory device, characterized by selecting at least one of the plurality of memory cells in the second mode, controlling the application of an operating voltage value ( Vdd ) from the sensing amplifier to a bit line connected to the selected memory cell, and controlling the application of a clamping voltage value ( Vcl ) from the clamping circuit to a bit line of the unselected memory cell to read data of the selected memory cell.
In Article 12, A method for driving a capacitorless semiconductor memory device, characterized in that, in the second mode above, the voltage of the selected word line is changed to 0V, and an operating voltage value ( Vdd ) is applied to the unselected word line, so that the voltage drop of the unselected memory cell does not exceed the threshold voltage value by the clamping voltage value.

Description

Semiconductor memory device and operating methods of the semiconductor memory device The present invention relates to semiconductor memory technology, and more specifically, to a semiconductor memory device and a method for operating the same. Today, Dynamic Random Access Memory (DRAM) is a semiconductor memory that writes and reads data randomly at high speeds and is widely used in data storage devices or equipment. DRAM comprises multiple repeated memory cells, each of which generally includes a capacitor configured to store data information and a transistor configured to control the reading of data information from the capacitor structure. To facilitate the integrated development of such memory cells, a technology using memory cells with a 2T0C structure has been developed in the relevant technology field. The 2T0C structure uses two transistors as memory devices and reduces the volume occupied by the memory cell by not including a capacitor. In addition, adjacent memory cells can be configured to share word lines and bit lines. However, this 2T0C DRAM has a problem in that it can be interfered with depending on the state of adjacent cells that share a word line and a bit line when reading a selected cell. For example, when a selected cell is off (data 0) and three adjacent cells are all on (data 1), a problem arises in which the probability of the selected cell being interfered with by the three adjacent cells increases. Therefore, there is a very urgent need to develop a 2TOC circuit that can solve the problem of interference between adjacent memory cells. In particular, according to today's technology trends, DRAM can be used not only as memory but also as a neuromorphic device for artificial intelligence, so in this case, it is even more necessary to develop a 2TOC circuit that can be used without data reading errors and exclude interference caused by adjacent cells. FIG. 1 is a drawing illustrating an embodiment of a capacitorless semiconductor device including two transistors according to the present invention. FIG. 2 is a drawing illustrating an embodiment of a memory cell array including a plurality of memory cells. FIG. 3 is a diagram illustrating an embodiment in which a semiconductor memory device according to the present invention operates in a first mode. FIG. 4 is a diagram illustrating an embodiment in which a semiconductor memory device according to the present invention operates in a second mode. FIG. 5 is a flowchart illustrating a method for driving a memory cell array including a plurality of memory cells including two transistors according to an embodiment of the present invention. Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. The embodiments of the present invention described below are provided to more clearly explain the present invention to those skilled in the art, and the scope of the present invention is not limited by the following embodiments, and the following embodiments may be modified in various other forms. The terms used herein are for describing specific embodiments and are not intended to limit the invention. Terms used herein in the singular form may include plural forms unless the context clearly indicates otherwise. Additionally, the terms “comprise” and/or “comprising” used herein specify the presence of the mentioned features, steps, numbers, actions, components, elements, and/or groups thereof, and do not exclude the presence or addition of one or more other features, steps, numbers, actions, components, elements, and/or groups thereof. Furthermore, the term “connected” used herein means not only that components are directly connected, but also includes the concept of indirectly connecting components through the interposition of additional components between them. Furthermore, when a component is described in this specification as being located "on" another component, this includes not only cases where a component is in contact with another component, but also cases where another component exists between the two components. The term "and/or" as used in this specification includes any one of the listed items and all combinations of one or more thereof. Additionally, terms of degree such as "about" and "substantially" as used in this specification are used to mean a range of numerical or degree or an approximation thereof, taking into account inherent manufacturing and material tolerances, and are used to prevent an infringer from unfairly exploiting the disclosures in which precise or absolute numerical values provided to aid in understanding this specification are mentioned. Embodiments of the present invention will be described in detail below with reference to the attached drawings. The sizes or thicknesses of the areas or parts depicted in the attached drawings may be slightly exaggerated for the clarity of the specification and convenience of explanation. Throughout the detailed descrip