KR-20260067150-A - Diode embedded Semiconductor memory device and Operating methods of the semiconductor memory device

Abstract

A capacitorless semiconductor memory device and a method of operating the capacitorless semiconductor memory device are disclosed. The disclosed capacitorless semiconductor memory device comprises a plurality of memory cells including a write transistor and a read transistor, and the read transistor may include a memory cell array including a drain region, a control electrode, and a source region; a diode connected to the source region of the read transistor; and a sensing amplifier connected to the read bit line. Additionally, the disclosed capacitorless semiconductor memory device may include a memory cell array comprising a plurality of memory cells including a write transistor and a read transistor; a bit line connected to the source region of the read transistor; and a sensing amplifier connected to the bit line, and the contact material of the source region of the read transistor may include a Schottky contact material.

Inventors

• 황철성

Assignees

• 서울대학교산학협력단

Dates

Publication Date

20260512

Application Date

20241105

Claims (13)

1. As a capacitorless semiconductor memory device, A memory cell array comprising a plurality of memory cells including a write transistor and a read transistor, wherein the read transistor includes a drain region, a control electrode, and a source region; A diode connected to the source region of the above-mentioned reading transistor; and Sensing amplifier connected to the above read bit line A capacitorless semiconductor memory device characterized by including
2. In Article 1, A capacitorless semiconductor memory device characterized by the fact that when an operating voltage value ( Vdd ) is applied to a non-selected memory cell among the memory cells included in the memory cell array, leakage current from the read word line to the read bit line is blocked by the diode.
3. In Article 1, It further includes a clamping circuit connected in parallel with the above-mentioned sensing amplifier, and The above clamping circuit is a capacitorless semiconductor memory device that makes the minimum value of the voltage of the above read bit line become the clamping voltage value.
4. In Article 1, A capacitorless semiconductor memory device characterized in that, when the read bit line voltage of an unselected memory cell among the memory cells is set to 0V and the read word line voltage is set to an operating voltage value ( Vdd ), the voltage value between the drain region and the source region of the unselected memory cell is the value obtained by subtracting the diode voltage value ( Vdiode ) from the operating voltage value ( Vdd ).
5. In Article 4, A capacitorless semiconductor memory device characterized in that the diode voltage value (V diode ) is set to be less than the clamping voltage value (V cl ) provided by the clamping circuit.
6. As a capacitorless semiconductor memory device, A memory cell array comprising a plurality of memory cells including a write transistor and a read transistor; A bit line connected to the source region of the above-mentioned read transistor; and Sensing amplifier connected to the above bit line Includes, A capacitorless semiconductor memory device in which the contact material of the source region of the above-mentioned read transistor includes a Schottky contact material.
7. In Paragraph 6, A capacitorless semiconductor memory device characterized in that the above-described read transistor includes an IGZO channel comprising at least one of indium, gallium, zinc, and oxygen.
8. In Article 6, A capacitorless semiconductor memory device characterized in that the contact material of the source region is a material having a work function of 4.7 eV or higher.
9. In Article 6, A capacitorless semiconductor memory device characterized in that the contact material of the source region is Ru, Au, Pt, Ni, Pt, or an alloy thereof.
10. In Article 6, A capacitorless semiconductor memory device characterized in that the contact material of the drain region is a material constituting an ohmic contact.
11. In Article 6, A capacitorless semiconductor memory device characterized by the drain region of the above-mentioned read transistor comprising at least one of Ti, TiN, Al, and alloys thereof.
12. In Article 6, A capacitorless semiconductor memory device characterized in that the above-described read transistor comprises an IGZO channel comprising at least one of indium, gallium, zinc, and oxygen, the contact material of the source region is Pt or a Pt alloy material, and the drain region is Ti or a Ti alloy material.
13. In Article 6, It further includes a clamping circuit connected in parallel with the above-mentioned sensing amplifier, and The above clamping circuit is a capacitorless semiconductor memory device that makes the minimum value of the voltage of the above read bit line become the clamping voltage value.

Description

Diode-embedded semiconductor memory device and operating methods of the semiconductor memory device The present invention relates to semiconductor memory technology, and more specifically, to a semiconductor memory device in which a diode is integrated and a method for driving the same. Today, Dynamic Random Access Memory (DRAM) is a semiconductor memory that writes and reads data randomly at high speeds and is widely used in data storage devices or equipment. DRAM comprises multiple repeated memory cells, each of which generally includes a capacitor configured to store data information and a transistor configured to control the reading of data information from the capacitor structure. To facilitate the integrated development of such memory cells, a technology using a 2T0C structure for memory cells has been developed in the relevant technology field. The 2T0C structure uses two transistors as memory elements and does not include a capacitor, thereby reducing the volume occupied by the memory cell. In addition, adjacent memory cells can be configured to share word lines and bit lines. However, this 2T0C DRAM has a problem in that it can be interfered with depending on the state of adjacent cells that share a word line and a bit line when reading a selected cell. For example, when a selected cell is off (data 0) and three adjacent cells are all on (data 1), a problem arises in which the probability of the selected cell being interfered with by the three adjacent cells increases. Therefore, there is a very urgent need to develop a 2TOC circuit that can solve the problem of interference between adjacent memory cells. In particular, according to today's technology trends, DRAM can be used not only as memory but also as neuromorphic devices for artificial intelligence, so in this case, it is even more necessary to develop a 2TOC circuit that can be used without data reading errors and exclude interference caused by adjacent cells. FIG. 1 is a drawing illustrating an embodiment of a capacitorless semiconductor device including two transistors according to the present invention. FIG. 2 is a drawing illustrating an embodiment of a memory cell array including a plurality of memory cells. FIG. 3 is a drawing illustrating a memory cell array including a diode that prevents leakage current according to an embodiment of the present invention. FIG. 4 is a drawing illustrating a memory cell array including a read transistor that prevents leakage current according to an embodiment of the present invention. FIG. 5 is a diagram illustrating the current flow when a reading transistor is configured with various contact materials according to an embodiment of the present invention. FIG. 6 is a diagram illustrating memory cell characteristics when a read transistor is configured with various contact materials according to an embodiment of the present invention. Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. The embodiments of the present invention described below are provided to more clearly explain the present invention to those skilled in the art, and the scope of the present invention is not limited by the following embodiments, and the following embodiments may be modified in various other forms. The terms used herein are for describing specific embodiments and are not intended to limit the invention. Terms used herein in the singular form may include plural forms unless the context clearly indicates otherwise. Additionally, the terms “comprise” and/or “comprising” used herein specify the presence of the mentioned features, steps, numbers, actions, components, elements, and/or groups thereof, and do not exclude the presence or addition of one or more other features, steps, numbers, actions, components, elements, and/or groups thereof. Furthermore, the term “connected” used herein means not only that components are directly connected, but also includes the concept of indirectly connecting components through the interposition of additional components between them. Furthermore, when a component is described in this specification as being located "on" another component, this includes not only cases where a component is in contact with another component, but also cases where another component exists between the two components. The term "and/or" as used in this specification includes any one of the listed items and all combinations of one or more thereof. Additionally, terms of degree such as "about" and "substantially" as used in this specification are used to mean a range of numerical or degree or an approximation thereof, taking into account inherent manufacturing and material tolerances, and are used to prevent an infringer from unfairly exploiting the disclosures in which precise or absolute numerical values provided to aid in understanding this specification are mentioned. Embodiments of the present invention will be described in detail below with refere