KR-20260067192-A - CHIP ON FILM PACKAGE AND ELECTRONIC DEVICE INCLUDING THE SAME

KR20260067192AKR 20260067192 AKR20260067192 AKR 20260067192AKR-20260067192-A

Abstract

A chip-on-film package according to an embodiment comprises a substrate, a semiconductor chip positioned on the substrate, a plurality of first wires extending from a portion overlapping with one edge of the semiconductor chip on the substrate to one edge of the substrate, a plurality of second wires extending from a portion overlapping with the other edge of the semiconductor chip to the other edge of the substrate, a plurality of first bumps connecting the plurality of first wires and the semiconductor chip, and a plurality of first dummy patterns spaced apart from at least some of the plurality of first bumps and positioned closer to the center of the semiconductor chip than the plurality of first bumps, wherein the plurality of first bumps include a plurality of first outer bumps spaced apart in a first direction parallel to one edge of the semiconductor chip, and a plurality of first inner bumps spaced apart in the first direction and positioned closer to the center of the semiconductor chip than the plurality of first outer bumps, and wherein the plurality of first dummy patterns can each be spaced apart from the plurality of first inner bumps and positioned in a second direction perpendicular to the first direction. there is.

Inventors

신나래
하정규

Assignees

삼성전자주식회사

Dates

Publication Date: 20260512
Application Date: 20241105

Claims (10)

substrate, A semiconductor chip located on the above substrate, A plurality of first wires extending from a portion overlapping with one edge of the semiconductor chip on the substrate to one edge of the substrate, A plurality of second wires extending from a portion overlapping with the other edge of the semiconductor chip to the other edge of the substrate, A plurality of first bumps connecting the plurality of first wires and the semiconductor chip, It includes a plurality of first dummy patterns spaced apart from at least some of the plurality of first bumps and located closer to the center of the semiconductor chip than the plurality of first bumps, The above plurality of first bumps are, It includes a plurality of first outer bumps spaced apart in a first direction parallel to one edge of the semiconductor chip, and a plurality of first inner bumps spaced apart in the first direction and located closer to the center of the semiconductor chip than the plurality of first outer bumps. A chip-on-film package, wherein the plurality of first dummy patterns are each spaced apart from the plurality of first inner bumps and in a second direction perpendicular to the first direction.
In Article 1, A chip-on-film package in which the plurality of first dummy patterns do not overlap with the plurality of first outer bumps in the second direction.
In Article 1, A chip-on-film package, wherein each of the plurality of first dummy patterns extends along the second direction and is spaced apart along the second direction from a centerline passing through the center of the semiconductor chip, and is located between the centerline and the first bumps.
In Article 1, A plurality of second bumps connecting the plurality of second wires and the semiconductor chip, and A chip-on-film package further comprising a plurality of second dummy patterns spaced apart from the plurality of second bumps in the second direction and positioned closer to the center of the semiconductor chip than the second bumps.
In Paragraph 4, The above second dummy patterns do not overlap with the above first dummy pattern in the above second direction, in a chip-on-film package.
In Paragraph 4, It further includes a third wire connecting any two of the plurality of first wires and the plurality of second wires. A chip-on-film package in which, among the plurality of first wires and the plurality of second wires, the first dummy pattern or the second dummy pattern is not located in the area overlapping in the second direction with the wire connected to the third wire.
In Article 1, The first wirings are spaced apart from each other along the first direction, and A chip-on-film package further comprising a third dummy pattern located on one side of the outermost wiring among the first wirings.
In Article 7, The above third dummy pattern extends along the above second direction, and A chip-on-film package in which the length of the third dummy pattern extending along the second direction is longer than or equal to the length of the first wiring extending along the second direction.
Printed circuit board, and A chip-on-film package including an output pin located on one side and an input pin located on the other side, and connected to the printed circuit board through the input pin, The above chip-on-film package is, substrate, A semiconductor chip located on the above substrate, A plurality of first wires extending from a portion overlapping with one edge of the semiconductor chip on the substrate to one edge of the substrate and connected to the output pin, A plurality of second wires extending from a portion overlapping with the other edge of the semiconductor chip to the other edge of the substrate and connected to the input pin, A plurality of first bumps connecting the plurality of first wires and the semiconductor chip, It includes a plurality of first dummy patterns spaced apart from at least some of the plurality of first bumps and located closer to the center of the semiconductor chip than the plurality of first bumps, The above plurality of first bumps are, It includes a plurality of first outer bumps spaced apart in a first direction parallel to one edge of the semiconductor chip, and a plurality of first inner bumps spaced apart in the first direction and located closer to the center of the semiconductor chip than the plurality of first outer bumps. An electronic device in which the plurality of first dummy patterns are each spaced apart from the plurality of first inner bumps and in a second direction perpendicular to the first direction.
substrate, A semiconductor chip located on the above substrate, A plurality of first wires extending from a portion overlapping with one edge of the semiconductor chip on the substrate to one edge of the substrate, A plurality of second wires extending from a portion overlapping with the other edge of the semiconductor chip to the other edge of the substrate, A first protective layer covering at least a portion of the first wirings and the second wirings, A second protective layer that fills the gap region between the substrate and the semiconductor chip, and A plurality of first bumps connecting the plurality of first wires and the semiconductor chip, A plurality of second bumps connecting the plurality of second wires and the semiconductor chip, and It includes a plurality of first dummy patterns spaced apart from at least some of the plurality of first bumps and located closer to the center of the semiconductor chip than the plurality of first bumps, The above plurality of first bumps are, It includes a plurality of first outer bumps spaced apart in a first direction parallel to one edge of the semiconductor chip, and a plurality of first inner bumps spaced apart in the first direction and located closer to the center of the semiconductor chip than the plurality of first outer bumps. A chip-on-film package, wherein each of the plurality of first dummy patterns has a rectangular shape extending in a second direction perpendicular to the first direction and is spaced apart from the plurality of first inner bumps in the second direction.

Description

Chip on Film Package and Electronic Device Including the Same The present disclosure relates to a chip-on-film package. In response to the recent trend of miniaturization, thinning, and lightweighting of electronic products, Chip On Film (COF) packaging technology using a flexible film substrate has been proposed as a high-density semiconductor chip mounting technology. COF packaging technology is attracting attention as a high-density packaging technology because the semiconductor chip can be directly bonded to the film substrate via flip-chip bonding and connected to an external circuit via short leads, and it is possible to form a dense wiring pattern. FIG. 1 is a schematic perspective view illustrating an electronic device including a chip-on-film package according to one embodiment. FIG. 2 is a block diagram schematically illustrating an electronic device including a chip-on-film package according to one embodiment. FIG. 3 is a plan view showing a chip-on-film package according to an embodiment. Figure 4 is a cross-sectional view of a chip-on-film package cut along I1-I1' of Figure 3. Figure 5 is an enlarged plan view of area 'A' in Figure 3. FIG. 6 is a plan view showing a chip-on-film package according to an embodiment. Figure 7 is a cross-sectional view of a chip-on-film package cut along I2-I2' of Figure 6. FIG. 8 is a plan view showing a chip-on-film package according to an embodiment. FIG. 9 is a plan view showing a chip-on-film package according to an embodiment. FIG. 10 is a plan view showing a chip-on-film package according to an embodiment. FIG. 11 is a plan view showing a chip-on-film package according to an embodiment. Hereinafter, various embodiments of the present invention will be described in detail with reference to the attached drawings so that those skilled in the art can easily implement the present invention. The present invention may be embodied in various different forms and is not limited to the embodiments described herein. To clearly explain the present invention, parts unrelated to the explanation have been omitted, and the same reference numerals are used for identical or similar components throughout the specification. Furthermore, the size and thickness of each component shown in the drawings are depicted arbitrarily for convenience of explanation, and thus the present invention is not necessarily limited to what is illustrated. Thicknesses have been enlarged in the drawings to clearly represent various layers and regions. Additionally, for convenience of explanation, the thickness of some layers and regions has been exaggerated in the drawings. Furthermore, when it is said that a part, such as a layer, membrane, region, or plate, is "on" or "on" another part, this includes not only the case where it is "directly above" the other part, but also the case where there is another part in between. Conversely, when it is said that a part is "directly above" another part, it means that there is no other part in between. Also, saying that a part is "on" or "on" a reference part means that it is located above or below the reference part, and does not necessarily mean that it is located "on" or "on" in the direction opposite to gravity. Furthermore, throughout the specification, when a part is described as "including" a certain component, this means that, unless specifically stated otherwise, it does not exclude other components but may include additional components. Additionally, throughout the specification, "planar" means when the subject part is viewed from above, and "cross-sectional" means when the cross-section obtained by vertically cutting the subject part is viewed from the side. FIG. 1 is a schematic perspective view illustrating an electronic device including a semiconductor package according to one embodiment. FIG. 2 is a schematic block diagram illustrating an electronic device including a semiconductor package according to one embodiment. The electronic device (1000) according to the embodiment may be a display device. Referring to FIGS. 1 and 2, the electronic device (1000) may include at least one chip-on-film package (100), a printed circuit board (400), and a display panel (500). The chip-on-film package (100) may be located between the printed circuit board (400) and the display panel (500). The printed circuit board (400) and the display panel (500) may be connected by the chip-on-film package (100). The chip-on-film package (100) may receive a signal output from the printed circuit board (400) and transmit it to the display panel (500). The chip-on-film package (100) may be a DDI (Display Driver IC) package including a semiconductor chip (210) for driving an electronic device (1000). However, it is not limited thereto, and the type of chip-on-film package (100) may be varied. In some embodiments, when the chip-on-film package (100) is used in combination with an electronic device other than a display device, the semiconductor chip (210) may be a semiconductor c