KR-20260067229-A - MODEM CHIP THAT PERFORMS CYCLIC REDUNDANCY CHECK USING INTERNAL MEMORY AND SYSTEM ON CHIP INCLUDING THE SAME

Abstract

A modem chip according to an exemplary embodiment of the present disclosure comprises, wherein the modem chip receives a codeword comprising a transmission block composed of a plurality of code blocks, a HARQ processing circuit configured to perform a HARQ (hybrid automatic repeat request) based processing operation on the codeword, and an internal memory configured to store data generated from a second cyclic redundancy check, wherein the HARQ processing circuit comprises, for the plurality of code blocks, a code block processing circuit configured to decode each code block and perform a first cyclic redundancy check for each decoded code block, and a codeword processing circuit configured to generate target blocks corresponding to the decoded code blocks based on a modular operation using a polynomial for the second cyclic redundancy check and perform the second cyclic redundancy check on the decoded transmission block, wherein the plurality of code blocks are divided into a plurality of memory management groups each comprising at least two code blocks, and the internal memory comprises a plurality of memory elements allocated one-to-one to each of the plurality of memory management groups.

Inventors

• 배지민

Assignees

• 삼성전자주식회사

Dates

Publication Date

20260512

Application Date

20241105

Claims (20)

1. In a modem chip, the modem chip receives a codeword comprising a transmission block composed of a plurality of code blocks, and A HARQ processing circuit configured to perform a HARQ (hybrid automatic repeat request) based processing operation on the above codeword; and It includes internal memory configured to store data generated from a second cyclic redundancy check, and The above HARQ processing circuit is, A code block processing circuit configured to decode each code block and perform a first cyclic redundancy check on each decoded code block for the plurality of code blocks above; and It includes a codeword processing circuit configured to perform the second cyclic redundancy check on the decoded transmission block by generating target blocks corresponding to the decoded code blocks based on modular operation using a polynomial for the second cyclic redundancy check, and The above plurality of code blocks are, It is divided into a plurality of memory management groups, each containing at least two code blocks, and The above internal memory is, A modem chip characterized by including a plurality of memory elements allocated one-to-one to each of the plurality of memory management groups.
2. In paragraph 1, Each of the above plurality of memory elements is, A modem chip characterized by being configured to have a capacity corresponding to the data size of the remainder generated by the modular operation for one target block.
3. In paragraph 1, Among the plurality of memory management groups above, the first memory management group includes a first code block and a second code block arranged sequentially, and Among the plurality of memory elements above, the first memory element is allocated to the first memory management group, and The above codeword processing circuit is, In the section where the second cyclic redundancy check is performed, the first memory element is further configured to be accessed based on the result of the first cyclic redundancy check for the decrypted first code block and the decrypted second code block, and memory management information corresponding to the first memory management group. A modem chip characterized in that the above memory management information includes the arrangement order between the first code block and the second code block and the address of the first memory element.
4. In paragraph 3, The above codeword processing circuit is, A modem chip characterized by being configured to write a first remainder generated by the modular operation on a first target block corresponding to the decoded first code block that has passed the first cyclic redundancy check to the first memory element, and to overwrite a second remainder generated by the modular operation on a second target block corresponding to the decoded second code block that has passed the first cyclic redundancy check to the first memory element.
5. In paragraph 3, The above codeword processing circuit is, A modem chip further configured to write a first remainder generated by the modular operation on a first target block corresponding to the decoded first code block that passed the first cyclic redundancy check to the first memory element, and to skip writing a second remainder generated by the modular operation on a second target block corresponding to the decoded second code block that failed the first cyclic redundancy check.
6. In paragraph 5, The above modem chip further receives the retransmitted second code block, and The above codeword processing circuit is, A modem chip further configured to overwrite the first memory element with the third remainder generated by the modular operation on the third target block corresponding to the second code block that has been retransmitted and decoded after passing the first cyclic redundancy check.
7. In paragraph 3, It further includes a register circuit including a first register, and The above codeword processing circuit is, A modem chip characterized by being configured to selectively access the first register based on the result of the first cyclic redundancy check and the memory management information in the section where the second cyclic redundancy check is performed.
8. In Paragraph 7, The above codeword processing circuit is, A modem chip characterized by being configured to skip writing a first remainder generated by the modular operation on a first target block corresponding to the decoded first code block that failed the first cyclic redundancy check, and to write a second remainder generated by the modular operation on a second target block corresponding to the decoded second code block that succeeded the second cyclic redundancy check to the first memory element.
9. In paragraph 8, The above modem chip further receives the retransmitted first code block, and The above codeword processing circuit is, A modem chip further configured to write third intermediate data generated by the modular operation on the third target block corresponding to the first code block that has been retransmitted and decoded after passing the first cyclic redundancy check to the first register.
10. In Paragraph 7, The storage capacity of the internal memory mentioned above is, A modem chip characterized by having a storage capacity larger than that of the above-mentioned register circuit.
11. In paragraph 1, The memory management group unit in the plurality of memory management groups above is, A modem chip characterized by conforming to a unit of code block groups that are retransmitted at once.
12. In paragraph 1, The above codeword processing circuit is, A modem chip further configured to determine whether the second cyclic redundancy check passes based on the final remainder corresponding to the last target block among the above target blocks.
13. In paragraph 1, The above code block processing circuit is, A modem chip further configured to store a decrypted second code block that passed the first cyclic redundancy check among the decrypted code blocks in an external memory, based on the fact that the decrypted first code block among the decrypted code blocks failed the first cyclic redundancy check.
14. In paragraph 1, The above decrypted code blocks are, It includes a first code block, a second code block, and a third code block processed sequentially by the above code block processing circuit, and The above target blocks are, A first target block including the above-mentioned first code block and zero bits; and A second target block comprising the second code block, zero bits, and a first remainder obtained by dividing the first target block by the polynomial; and A modem chip characterized by including the above-mentioned third code block, zero bits, and a third target block including the second remainder obtained by dividing the above-mentioned second target block by the above-mentioned polynomial.
15. In a modem chip, the modem chip is configured to communicate with an external memory via a bus, and A HARQ processing circuit configured to perform HARQ-based processing operations on a codeword including a transmission block composed of a plurality of code blocks; and It includes an internal memory configured to assist the operation of the above HARQ processing circuit, and The above HARQ processing circuit is, A code block processing circuit configured to decode each code block for the plurality of code blocks above and to perform a first cyclic redundancy check on the decoded code blocks using the external memory; and It includes a codeword processing circuit configured to perform a second cyclic redundancy check for a decoded transmission block using the internal memory based on target blocks corresponding to the decoded code blocks, and The above plurality of code blocks are, It is divided into a plurality of memory management groups, each containing at least two code blocks, and The above internal memory is, A modem chip characterized by including a plurality of memory elements allocated one-to-one to each of the plurality of memory management groups.
16. In paragraph 15, The above codeword processing circuit is, A modem chip further configured to store a first valid remainder among the remainders corresponding to the above target blocks in the internal memory based on memory management information regarding the plurality of memory management groups.
17. In Paragraph 16, The above memory management information is, A modem chip characterized by including a code block, a mapping table including the order of placement of the code block in a memory management group to which the code block belongs, and the address of a memory element assigned to the code block.
18. In Paragraph 16, It further includes a register circuit comprising at least one register configured to be used in the above-mentioned second cyclic redundancy check, and The above codeword processing circuit is, A modem chip further configured to store a second valid remainder among the remainders corresponding to the above target blocks in the at least one register based on the memory management information.
19. In Paragraph 18, The above internal memory corresponds to volatile memory, and A modem chip characterized by at least one register corresponding to a flip-flop.
20. A modem configured to include internal memory composed of multiple memory elements and to support HARQ functionality; A processor configured to perform a predetermined data processing operation; and The above modem is, It is further configured to store intermediate data generated in a second cyclic redundancy check for a transmission block performed using a target block corresponding to a decoded first code block that passed the first cyclic redundancy check in the internal memory based on memory management information corresponding to the first code block. The above memory management information is, A modem chip characterized by including the placement order in the memory management group to which the first code block belongs and the address of the memory element assigned to the first code block.

Description

Modem chip that performs cyclic redundancy check using internal memory and system-on-chip including the same The technical concept of the present disclosure is an invention relating to a modem chip that decodes a codeword and performs a cyclic redundancy check on the decoded codeword, and a system-on-chip including the same. In a communication system, a transmitting device may transmit a codeword to a receiving device that includes a transmission block composed of code blocks. The codeword may include cyclic redundancy check (CRC) bits for a cyclic redundancy check per code block (hereinafter referred to as the first cyclic redundancy check) and transport block cyclic redundancy check (TBCRC) bits for a cyclic redundancy check for a transmission block (hereinafter referred to as the second cyclic redundancy check). The modem of the receiving device can decode the received codeword by code block, perform a first cyclic redundancy check for each decoded code block, and perform a second cyclic redundancy check on the decoded transmission block to determine whether the decoding of the received codeword was successful. Meanwhile, when there are code blocks among the decoded code blocks that fail the first cyclic redundancy check, the modem may request the transmitting device to retransmit the corresponding code blocks in units of code block groups, and the decoded code blocks that pass the first cyclic redundancy check may be stored in external memory. Subsequently, the modem may read the decoded code blocks from the external memory, generate a decoded transmission block by concatenating the decoding result of the retransmitted code block with the read decoded code blocks, and perform a second cyclic redundancy check on the decoded transmission block. Meanwhile, since external memory is used by processors other than the modem of the receiving device, the buses connecting the external memory to the modem and the processor, respectively, may become busy due to the processor, temporarily making communication between the modem and the external memory via the bus difficult. Furthermore, as the data size of decoded code blocks stored in external memory increases with the advancement of communication technology, the modem's access to external memory for the second cyclic redundancy check can increase the burden on the bus and the external memory. Consequently, a problem arose where the second cyclic redundancy check for the modem's decoded transmission blocks could not be completed within a predetermined time, which could ultimately lead to performance degradation of the modem. FIG. 1 is a block diagram schematically illustrating a system-on-chip according to an exemplary embodiment of the present disclosure. Figure 2 is a diagram for explaining codewords. FIG. 3 is a flowchart for explaining the operation method of a HARQ processing circuit according to an exemplary embodiment of the present disclosure. FIG. 4 is a block diagram showing a modem according to an exemplary embodiment of the present disclosure. FIGS. 5A and FIGS. 5B are drawings for illustrating embodiments utilizing internal memory in a second cyclic redundancy check according to exemplary embodiments of the present disclosure. FIGS. 6A and FIGS. 6B are drawings for illustrating a second cyclic redundancy check using internal memory according to an exemplary embodiment of the present disclosure. FIG. 7 is a flowchart for explaining a method of operation of a modem according to an exemplary embodiment of the present disclosure. FIGS. 8A and FIGS. 8B are drawings for illustrating a second cyclic redundancy check using internal memory according to an exemplary embodiment of the present disclosure. FIGS. 9A and 9B are drawings for specifically illustrating a second cyclic redundancy check of a modem chip according to an exemplary embodiment of the present disclosure. FIGS. 10A and FIGS. 10B are drawings for illustrating a second cyclic redundancy check using internal memory according to an exemplary embodiment of the present disclosure. FIGS. 11A and FIGS. 11B are drawings for specifically illustrating a second cyclic redundancy check of a modem chip according to an exemplary embodiment of the present disclosure. FIG. 12 is a diagram for explaining the relationship between a section where a first cyclic redundancy check is performed and a section where a second cyclic redundancy check is performed, according to an exemplary embodiment of the present disclosure. FIG. 13 is a block diagram showing a CB connection & TBCRC circuit according to an exemplary embodiment of the present disclosure. FIG. 14 is a flowchart for explaining the operation method of a HARQ processing circuit according to an exemplary embodiment of the present disclosure. FIG. 15 is a block diagram showing an electronic device according to an exemplary embodiment of the present disclosure. FIG. 16 is a drawing showing communication devices configured to perform a second cyclic redundancy che