KR-20260067239-A - SEMICONDUCTOR PACKAGE

KR20260067239AKR 20260067239 AKR20260067239 AKR 20260067239AKR-20260067239-A

Abstract

The technical concept of the present invention provides a semiconductor package comprising: a package substrate; a stacked structure mounted on the package substrate; and a heat dissipation structure disposed on the stacked structure; wherein the stacked structure comprises a lower die, a passive component chip disposed spaced apart from each other on the lower die, a second upper die, and a first upper die disposed on the passive component chip, wherein the lower die comprises a voltage regulator chip, the passive component chip comprises a capacitor, and the package substrate comprises an inductor.

Inventors

황지수
김소영

Assignees

삼성전자주식회사
성균관대학교산학협력단

Dates

Publication Date: 20260512
Application Date: 20241105

Claims (10)

Package substrate; A stacked structure mounted on the above package substrate; and A heat dissipation structure disposed on the above-mentioned laminated structure; comprising, The above laminated structure is, It includes a lower die, a passive component chip spaced apart from each other and a second upper die, and a first upper die disposed on the passive component chip. The above lower die includes a voltage regulator chip, and The above passive component chip includes a capacitor, and The above package substrate is characterized by including an inductor. Semiconductor package.
In paragraph 1, A semiconductor package characterized in that the upper surface of the first upper die is positioned at the same vertical level as the upper surface of the second upper die.
In paragraph 1, A semiconductor package characterized in that the lower die above includes a bridge inside.
In paragraph 3, The above bridge is, A semiconductor package characterized in that both ends are respectively connected to the connection bump of the passive component chip and the connection bump of the second upper die.
In paragraph 1, The above voltage regulation chip and the above inductor are, Characterized by being positioned such that, from a planar perspective, at least a portion overlaps with the above-mentioned passive component chip. Semiconductor package.
In paragraph 1, A semiconductor package characterized in that the height of the above passive component chip is smaller than the height of the above first upper die.
In paragraph 1, A semiconductor package characterized in that the above capacitor is a decoupling capacitor and an output capacitor of the above voltage regulation chip.
Package substrate; A lower die mounted on the above package substrate; A passive component chip mounted on the lower die and having a capacitor; At least one second upper die mounted on the lower die and disposed adjacent to the passive component chip; A first upper die disposed on the above passive component chip; and A heat dissipation structure disposed on the first upper die and at least one second upper die; comprising The above package substrate includes an inductor inside, and The lower die is characterized by including a voltage regulator chip inside and a bridge electrically connecting the first upper die and at least one second upper die. Semiconductor package.
In paragraph 8, The above inductor is positioned within the package substrate such that at least a portion overlaps with the passive component chip in a planar view, and The voltage regulation chip is characterized by being positioned within the lower die such that at least a portion of it overlaps with the passive component chip in a planar view. Semiconductor package.
A package substrate having an inductor inside; A lower die having a voltage regulator chip mounted on the above package substrate and positioned adjacent to the inductor in a planar view; A passive component chip mounted on the lower die and having a capacitor; A first upper die disposed on the above passive component chip; At least one second upper die mounted on the lower die, disposed adjacent to the passive component chip, and having an upper surface disposed at the same vertical level as the upper surface of the first upper die; A first sealant filling the space between the above passive element chip, the first upper die, and the at least one second upper die; A heat dissipation structure disposed on the first upper die and at least one second upper die; and A second sealant covering the upper surface of the package substrate, the lower die, the passive component chip, the first upper die, the at least one second upper die, and the heat dissipation structure; comprising The first upper die and the at least one second upper die are electrically connected by a bridge included inside the lower die, characterized in that Semiconductor package.

Description

Semiconductor Package {SEMICONDUCTOR PACKAGE} The technical concept of the present invention relates to a semiconductor package. More specifically, the present invention relates to a semiconductor package comprising an IVR (Integrated Voltage Regulator) chip. Voltage regulators (VRs) are widely used to regulate voltage in electronic devices such as computers, servers, and smartphones. Requirements for regulated voltage levels and current draw can vary significantly across different or even similar electronic devices. Typically, specific voltage regulators are designed for small-scale systems based on the input current requirements of those systems. Because manufacturing these voltage regulators within a semiconductor chip is difficult or costly, they are generally fabricated separately and placed on a board for use. Meanwhile, inductors and capacitors are required for the operation of voltage regulators, and these components are also placed on the board. FIG. 1 is a cross-sectional view of a semiconductor package according to one embodiment of the present invention. Figure 2 is a cross-sectional view showing an enlarged view of the capacitor portion within the passive component chip in the semiconductor package of Figure 1. FIGS. 3a and FIGS. 3b are a cross-sectional view and a perspective view, respectively, showing an enlarged view of the inductor portion of the semiconductor package of FIG. 1. FIGS. 4 to 8 are cross-sectional views illustrating a part of the manufacturing process of a semiconductor package according to one embodiment of the present invention. FIG. 9 is a cross-sectional view of a semiconductor package according to another embodiment of the present invention. Preferred embodiments of the present invention will be described in detail below with reference to the attached drawings. Identical components in the drawings are denoted by the same reference numerals, and redundant descriptions thereof are omitted. The embodiments are subject to various modifications and may have various examples; therefore, specific embodiments are illustrated in the drawings and described in detail in the detailed description. However, this is not intended to limit the scope of specific embodiments, and it should be understood that it includes all modifications, equivalents, and substitutions that fall within the scope of the disclosed concept and technology. In describing the embodiments, detailed descriptions of related prior art are omitted if it is determined that such detailed descriptions may obscure the gist of the matter. FIG. 1 is a cross-sectional view of a semiconductor package according to an exemplary embodiment of the present invention. FIG. 2 is a cross-sectional view showing an enlarged view of a capacitor portion within a passive component chip in the semiconductor package of FIG. 1, FIG. 3a and FIG. 3b are a cross-sectional view and a perspective view showing an enlarged view of an inductor portion in the semiconductor package of FIG. 1, FIG. 3a corresponds to a cross-section cut along the line I - I' in FIG. 3b. Referring to FIG. 1, the semiconductor package (100) of the present embodiment may include a package substrate (110), a passive component chip (130), a first upper die (120), a second upper die (140), a lower die (150), a first sealing material (160), a heat dissipation structure (170), a second sealing material (180), and an external connection terminal (190). The semiconductor package (100) of the present embodiment may be an Integrated Voltage Regulator (IVR) package including an inductor and a capacitor. Specifically, the package substrate (110) may be formed based on a ceramic substrate, a PCB, an organic substrate, an interposer substrate, etc. Additionally, according to an embodiment, the package substrate (110) may be formed based on an active wafer such as a silicon wafer. Specifically, the package substrate (110) may include a substrate body layer (112), a wiring layer (114), and an inductor (In.). The substrate body layer (112) may include an insulating material, such as a thermosetting resin like epoxy resin or a thermoplastic resin like polyimide, and may further include an inorganic filler. Additionally, the substrate body layer (112) may include prepreg, ABF (Ajinomoto Build-up Film), or FR-4, BT (Bismaleimide Triazine) resin, or PID (Photo Imageable Dielectric) resin, and may further include an inorganic filler. The wiring layer (114) may include rewiring lines and vias. The rewiring lines may be formed in a multilayer structure, and wiring lines between adjacent layers may be connected to each other through vias. An external connection terminal (190) may be disposed on the lower surface of the substrate body layer (112). The external connection terminal (190) may be disposed on an external connection pad and connected to the wiring layer (114) through the external connection pad. Additionally, the external connection terminal (190) may be connected to dies (e.g., first