KR-20260067240-A - SEMICONDUCTOR PACKAGE

Abstract

The technical concept of the present invention provides a semiconductor package comprising: a base chip; a plurality of first semiconductor chips stacked on the base chip; a dummy chip stacked on the uppermost first semiconductor chip among the plurality of first semiconductor chips; and a molding member surrounding the base chip, the first semiconductor chips, and the dummy chip; wherein the dummy chip includes a channel extending from the upper surface to the lower surface of the dummy chip, and the channel has a shape extending along the horizontal direction from the center of the dummy chip to at least one point located at the edge when viewed from above in a vertical direction, and the molding member fills the channel.

Inventors

• 이현민
• 신형철

Assignees

• 삼성전자주식회사

Dates

Publication Date

20260512

Application Date

20241105

Claims (10)

1. Base chip; A plurality of first semiconductor chips stacked on the base chip; A dummy chip stacked on the uppermost first semiconductor chip among the plurality of first semiconductor chips; and A molding member that encloses the base chip, the first semiconductor chips, and the dummy chip; comprising, The above dummy chip includes a channel extending from the upper surface to the lower surface of the dummy chip, and The above channel has a shape that extends along the horizontal direction from the center of the dummy chip to at least one point located at the edge when viewed from above in the vertical direction, and A semiconductor package characterized by the above-mentioned molding member filling the above-mentioned channel.
2. In paragraph 1, A semiconductor package characterized by the above channel having a combined shape of an X-shape extending from the center of the dummy chip to the four vertices of the dummy chip when viewed from above in a vertical direction, and a square ring shape that partially overlaps with the X-shape.
3. In paragraph 1, A semiconductor package characterized in that, when viewed from above in a vertical direction, the channel has a combined shape of a plus shape extending from the center of the dummy chip to each of the centers of the four sides of the dummy chip, and a square ring shape that partially overlaps with the plus shape.
4. In paragraph 1, A semiconductor package characterized in that, when viewed from above in a vertical direction, the channel has a combined shape of an X-shape extending from the center of the dummy chip to the four vertices of the dummy chip, a plus shape extending from the center of the dummy chip to the centers of each of the four sides of the dummy chip, and a square ring shape.
5. In paragraph 1, A semiconductor package characterized in that the horizontal width of the above channel changes according to the vertical level.
6. In paragraph 5, The cross-section along the XZ plane of the above channel has a trapezoidal shape, and A semiconductor package characterized by the above trapezoid having a tapered shape in which the horizontal width decreases as the vertical level decreases.
7. In paragraph 1, A semiconductor package characterized in that the upper surface of the molding member filling the channel forms a co-surface with the upper surface of the dummy chip.
8. Base chip; A plurality of first semiconductor chips stacked on the base chip; and A dummy chip having a channel extending vertically upward from the bottom surface, which is stacked on the uppermost first semiconductor chip among the plurality of first semiconductor chips; The above channel extends from the center of the dummy chip to at least four points located on the edge of the dummy chip when viewed from above in a vertical direction, and The first semiconductor chips mentioned above are stacked through direct bonding, and A semiconductor package characterized in that the above dummy chip is not electrically connected to the above first semiconductor chip.
9. First substrate; A base chip disposed on the first substrate; A plurality of first semiconductor chips stacked on the base chip; A dummy chip stacked on the uppermost first semiconductor chip among the plurality of first semiconductor chips and having a channel extending vertically upward from the lower surface to the upper surface; A first molding member that surrounds the base chip, the first semiconductor chips, and the dummy chip, and fills the channel; and It includes a first molding member and a second molding member wrapping the sides of each of the base chip on the first substrate; A semiconductor chip pad and a dielectric layer covering the side of the semiconductor chip pad are provided on each of the lower surface and the upper surface of the first semiconductor chips, and The above channel has a shape that extends along the horizontal direction from the center of the dummy chip to at least four points located at the edge when viewed from above in the vertical direction, and A semiconductor package characterized in that the upper surface of the first molding member has a common surface with the upper surface of the dummy chip.
10. In Paragraph 9, An interposer interposed between the first substrate and the base chip, and A semiconductor package characterized by further including a second semiconductor chip positioned horizontally spaced apart from the base chip on the interposer.

Description

Semiconductor Package The present invention relates to a semiconductor package, and more specifically, to a semiconductor package comprising a plurality of semiconductor chips stacked in a vertical direction. Recently, the demand for portable devices in the electronics market has been rapidly increasing, leading to a continuous demand for the miniaturization and lightweighting of electronic components mounted on these products. To achieve this miniaturization and lightweighting, the semiconductor packages installed in them are required to have increasingly smaller volumes while processing high-capacity data and minimizing defects. In addition, semiconductor packages that stack multiple semiconductor chips vertically are being developed to reduce the size of the semiconductor package. However, as multiple semiconductor chips are hybrid-bonded, issues regarding the structural reliability of the semiconductor package are emerging. FIG. 1 is a plan view schematically showing a semiconductor package according to exemplary embodiments of the present invention. Figure 2 is a cross-sectional view along the line X1-X1' of the semiconductor package of Figure 1. FIG. 3 is a plan view schematically showing a semiconductor package according to exemplary embodiments of the present invention. Figure 4 is a cross-sectional view along the line X1-X1' of the semiconductor package of Figure 3. FIG. 5 is a plan view schematically showing a semiconductor package according to exemplary embodiments of the present invention. Figure 6 is a cross-sectional view along the line X1-X1' of the semiconductor package of Figure 5. FIG. 7 is a plan view schematically showing a semiconductor package according to exemplary embodiments of the present invention. Figure 8 is a cross-sectional view along the line X1-X1' of the semiconductor package of Figure 7. FIGS. 9 to 12b are cross-sectional views illustrating a method for manufacturing semiconductor packages according to exemplary embodiments of the present invention. FIG. 13 is a cross-sectional view schematically illustrating a semiconductor package according to exemplary embodiments of the present invention. FIG. 14 is a cross-sectional view schematically illustrating a semiconductor package according to exemplary embodiments of the present invention. FIG. 15 is a cross-sectional view schematically illustrating a semiconductor package according to exemplary embodiments of the present invention. Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Identical components in the drawings are denoted by the same reference numerals, and redundant descriptions thereof are omitted. FIG. 1 is a plan view schematically illustrating a semiconductor package according to exemplary embodiments of the present invention. FIG. 2 is a cross-sectional view along the line X1-X1' of the semiconductor package of FIG. 1. Referring to FIGS. 1 and FIGS. 2, the semiconductor package (10) may include a chip stacking structure (200) and a first molding member (390). The chip stacking structure (200) may include a base chip (220), a first semiconductor chip (210), and a dummy chip (230). The base chip (220) may be a chip located at the bottom of the chip stacking structure (200). According to exemplary embodiments, the base chip (220) may integrate signals from a plurality of first semiconductor chips (210) stacked on top of the base chip (220) and transmit them externally, or transmit signals and power from the outside to the first semiconductor chips (210). Accordingly, the base chip (220) may be referred to herein as a buffer chip or a control chip. According to exemplary embodiments, the base chip (220) may have a larger footprint than the first semiconductor chip (210) as shown in FIG. 2, but is not limited thereto, and the base chip (220) may have substantially the same footprint as the first semiconductor chip (210). That is, the base chip (220) may be larger than the size of the first semiconductor chip (210) or substantially the same size as the first semiconductor chip (210). The base chip (220) may include various types of individual devices. The individual devices may include various microelectronics devices, such as a MOSFET (metal-oxide-semiconductor field effect transistor) such as a CMOS transistor (complementary metal-insulator-semiconductor transistor), a system LSI (large scale integration), an image sensor such as a CIS (CMOS imaging sensor), a MEMS (micro-electro-mechanical system), active devices, passive devices, etc. In some embodiments, the base chip (220) may not include memory cells. For example, the semiconductor devices included in the base chip (220) may include a serial-parallel conversion circuit, a test logic circuit such as a DFT (design for test), a JTAG (Joint Test Action Group), a MBIST (memory builtin self-test), and a signal interface circuit such as a PHY. The first semiconductor chip (210) can be stacked in a