KR-20260067277-A - SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR PACKAGE ASSEMBLY WITH EDGE INTERCONNECTION AND METHOD OF FORMING THE SAME

Abstract

An IC stack comprises a plurality of integrated circuit (IC) structures horizontally separated from one another, wherein each IC structure comprises an upper surface, a lower surface opposite to the upper surface, and four sidewalls having a first sidewall, a second sidewall, a third sidewall, and a fourth sidewall; wherein the area of the lower surface or the upper surface is larger than the area of the sidewalls; an RDL structure extending laterally covering each of the first sidewalls of the plurality of IC structures; and a thermally conductive layer extending upward between two adjacent IC structures.

Inventors

• 통 호-밍
• 루 차오-춘

Assignees

• 엔디-에이치아이 테크놀로지스 랩 아이엔씨
• 에트론 테크놀로지, 아이엔씨.

Dates

Publication Date

20260512

Application Date

20250221

Priority Date

20241105

Claims (20)

1. In IC stacks, A plurality of integrated circuit (IC) structures horizontally separated from one another, wherein each IC structure comprises an upper surface, a lower surface opposite to the upper surface, and four sidewalls having a first sidewall, a second sidewall, a third sidewall, and a fourth sidewall; wherein the area of the lower surface or the upper surface is larger than the area of the sidewalls; An RDL structure extending to the side covering each of the first sidewalls of the plurality of IC structures above; and It includes a thermal conductivity layer extending upward between two adjacent IC structures; An IC stack in which the thermal conductivity of the thermally conductive layer extending upward is higher than the thermal conductivity of Si.
2. The IC stack of claim 1 further comprises a laterally extending thermal conductive layer covering each of the second sidewalls of the plurality of IC structures and thermally coupled to the laterally extending thermal conductive layer, wherein the laterally extending RDL structure is opposite to the laterally extending thermal conductive layer and the thermal conductivity of the laterally extending thermal conductive layer is higher than the thermal conductivity of Si.
3. In claim 2, the thermal conductive layer extending upward or the thermal conductive layer extending sideways comprises BN, AlN, W, SiC, or copper, in an IC stack.
4. An IC stack according to claim 1, further comprising an upwardly extending RDL structure covering each of the third sidewalls of the plurality of IC structures, wherein the upwardly extending RDL structure is electrically connected to the sidely extending RDL structure.
5. In claim 4, each IC structure includes a DRAM semiconductor die, and the IC stack is an HBM compatible structure.
6. In claim 4, the IC stack further comprises a logic control chip electrically connected under an RDL structure extending to the side of the IC stack.
7. In claim 6, each of the IC structures comprises a DRAM semiconductor die comprising a plurality of memory I/O pads, the logic control chip comprises a plurality of logic I/O pads, and the plurality of memory I/O pads of each DRAM semiconductor die are electrically coupled to the plurality of logic I/O pads through a laterally extending RDL structure, an IC stack.
8. In claim 7, the memory I/O pads do not include electrostatic discharge (ESD) protection circuits, or each DRAM semiconductor die includes a plurality of row address pads and a plurality of column address pads physically independent of the plurality of row address pads, in an IC stack.
9. In claim 7, each DRAM semiconductor die further comprises a plurality of external bidirectional repeaters, wherein the bidirectional repeater of the second DRAM semiconductor die is electrically coupled to a corresponding bidirectional repeater of the first DRAM semiconductor die through a second metal line of the RDL structure extending laterally or the RDL structure extending upwardly, and the corresponding bidirectional repeater of the first DRAM semiconductor die is electrically coupled to a corresponding logic I/O pad of the logic control chip through a first metal line of the RDL structure extending laterally or the RDL structure extending upwardly, IC stack.
10. In claim 7, each DRAM semiconductor die further comprises a plurality of external bidirectional repeaters, wherein the bidirectional repeater of the first DRAM semiconductor die is electrically coupled to a corresponding logic I/O pad of the logic control chip through a first metal line of the RDL structure extending laterally or the RDL structure extending upwardly, and the corresponding bidirectional repeater of the second DRAM semiconductor die is electrically coupled to a corresponding logic I/O pad of the logic control chip through a second metal line of the RDL structure extending laterally or the RDL structure extending upwardly, IC stack.
11. In claim 1, the first IC structure of the plurality of IC structures is A first semiconductor body having a first primary surface and a first secondary surface, wherein the first primary surface is substantially perpendicular to the first secondary surface; and The interconnect structure comprises a primary redistribution layer (RDL) on the first primary surface, wherein the primary RDL has a second secondary surface aligned with the first secondary surface of the first semiconductor body; An IC stack, wherein the first secondary surface and the second secondary surface together form a secondary plane, and the first RDL further comprises a first conductive element exposed through the second secondary surface of the first RDL.
12. In claim 11, the first conductive element comprises a conductive pad on the surface of the primary RDL structure substantially parallel to the first primary surface, a conductive via connecting adjacent layers of the primary RDL, a loaded via across the primary RDL, or a combination thereof, an IC stack.
13. In claim 12, the IC stack comprises, wherein the first semiconductor body includes at least a silicon through-via, a molding through-via, or an insulating element exposed through the first secondary surface.
14. In claim 11, the IC stack comprises a plurality of first dies disposed on the same package layer, a second die stacked vertically, a second die stacked vertically disposed alongside another third die on the same package layer, or a combination thereof.
15. In claim 14, the IC stack comprises a plurality of conductive vias, fillers or plugs of the same or different lengths, wherein the first semiconductor body electrically connects the plurality of first dies to the primary RDL and/or the RDL structure extending to the side.
16. In claim 11, the laterally extending RDL structure is electrically connected to a first conductive element of the primary RDL, to a conductive via, filler, or plug within the first semiconductor body, or a combination thereof; and the laterally extending RDL structure comprises a hybrid bonding layer or a bump pad array, IC stack.
17. In IC stacks, A plurality of integrated circuit (IC) structures horizontally separated from one another, wherein each IC structure comprises an upper surface, a lower surface opposite to the upper surface, and four sidewalls having a first sidewall, a second sidewall, a third sidewall, and a fourth sidewall; wherein the area of the lower surface or the upper surface is larger than the area of the sidewalls; A set of thermally conductive layers extending upward, wherein the corresponding thermally conductive layer extending upward is disposed between two adjacent IC structures of the plurality of IC structures; and It includes a first-side extending thermal conductive layer that covers each of the second sidewalls of the plurality of IC structures and is thermally coupled to the set of thermal conductive layers extending upward; IC stack, in which the thermal conductivity of the thermal conductive layer extending upward and/or the thermal conductive layer extending laterally is higher than the thermal conductivity of Si.
18. In claim 17, an IC stack further comprising an RDL structure extending to a side covering each first side of the plurality of IC structures.
19. In claim 18, each IC structure comprises a DRAM semiconductor die, and the IC stack further comprises a logic control chip electrically connected under an RDL structure extending to the side of the IC stack; the IC stack is an HBM compatible structure.
20. In claim 17, the IC stack further comprises a second-side extending thermal conductive layer covering each third sidewall of the plurality of IC structures, wherein the second-side extending thermal conductive layer is thermally coupled to the set of upper-side extending thermal conductive layers.

Description

Semiconductor Package and Semiconductor Package Assembly with Edge Interconnection and Method of Forming the Same The present disclosure generally relates to a semiconductor device and a method for forming the same, and more specifically to a semiconductor device having lateral edge interconnections and a method for forming the same. Tremendous progress has been made in the two-dimensional (2D) geometric scaling of conventional transistors due to great achievements in engineering and materials science, including highly complex multi-stage lithography patterning, new strain-enhancing materials, and metal oxide gates. However, as the aforementioned technologies approach practical limits, 2D device scaling is losing momentum. Three-dimensional integrated circuit (3D IC) integration, which represents a radical departure from traditional 2D IC integration, is recognized as a next-generation semiconductor technology that simultaneously achieves high performance, low power consumption, small physical size, and high integration density. 3D ICs provide a pathway to continuously meet the performance and cost requirements of next-generation devices while allowing for looser gate lengths and lower process complexity for high-end applications such as high-performance computing (HPC), data centers, and artificial intelligence (AI). 3D IC integration can be carried out through the following. - Monolithic integration and/or - Vertical integration of heterogeneous dies. 3D monolithic integration typically involves the vertical integration of multiple active silicon layers and vertical interconnection between the layers. Recently, "CPU cache (cache-on-central processing unit)" 3D IC structures using copper hybrid bonding have been demonstrated and commercialized. Today, high-bandwidth memory (HBM) dynamic random-access memory (DRAM) stacks, each created by vertically integrating multiple DRAM dies into a control IC, represent the largest volume of commercial 3D ICs today. These HBM DRAM stacks are typically mounted alongside processor ICs on silicon interposers in 2.5D IC packaging (Fig. 1a) for high-end applications such as HPC, data centers, and AI. 2.5D ICs typically include active dies, such as DRAM and control ICs, and through-silicon vias (TSVs) on the silicon interposer, which can be passive or active. 2.5D ICs may include a redistribution layer (RDL) on the interposer and active die. Taking ChatGPT as an example, it is powered by nVidia's H100 GPU in a 2.5D IC configuration. Moving forward, 3D ICs can enable memory-on-memory, logic-over-memory, and logic-over-logic structures using interconnection technologies that include TSVs, RDLs containing interconnect wiring and microvias, flip-chip bonding based on copper filler microbumps or solder bumps, as well as newly emerging copper hybrid bonding technologies. 3D ICs created through monolithic and/or heterogeneous integration allow for the vertical stacking of heterogeneous dies and/or active silicon layers across various manufacturing processes and nodes, chip/chiplet reuse, and chiplets within a SiP (System in Package). Ultimately, 3D IC integration can stack HBM DRAM onto a processor, significantly reducing data transfer times between the DRAM die and the processor and substantially narrowing the peak computing memory bandwidth gap. 3D ICs are ideal for applications that require integrating more transistors into a given footprint (Mobile System-on-Chip, SoC) or for applications that have already exceeded the functional limits of a single die at cutting-edge nodes, such as HPC, data centers, AI/machine learning, 5G/6G networks, graphics, smartphones/wearables, automotive, and other applications requiring ultra-high performance, high-power efficiency devices. These devices include CPUs, GPUs (Graphics Processing Units), FPGAs (Field Programmable Gate Arrays), ASICs (Application-Specific ICs), TPUs (Tensor Processing Units), integrated photonics, APs (Application Processors for Mobile Phones), packet buffer/router devices, etc. To accelerate adoption, 3D IC systems must be designed in a holistic manner through IC-package-system co-design, which includes silicon IP, IC/chiplets, and IC packages, and the associated power and thermal issues must be addressed. In contrast to PPAC (Performance, Power, Area, and Cost) optimization per square centimeter applied to 2D packaging, IC-package-system co-design for 3D ICs aims to achieve "PPAC optimization per cubic millimeter," where vertical dimensions, including the IC, interposer, IC package substrate, IC package, and system printed circuit board (PCB), must all be considered in all trade-off decisions. Today, all 3D ICs adopt packaging topologies featuring sectional electrical interconnections, for example, from the bottom of the control IC in an HBM DRAM stack connected to an interposer to the DRAM die above the control IC, or from the stacked substrate to the bottom of the CPU in a cache-on-CPU. When powering 3D ICs that rely