KR-20260067307-A - HIGH BANDWIDTH MEMORY STACK WITH SIDE EDGE INTERCONNECTION AND 3D IC STRUCTURE WITH THE SAME

Abstract

The IC structure comprises a memory stack containing semiconductor dies horizontally separated from one another, wherein each semiconductor die has an upper surface, a lower surface, four sidewalls, and a plurality of edge pads arranged along the sidewalls. The IC structure further comprises a memory controller located below the first memory stack and electrically connected to the edge pads of each semiconductor die, a processor circuit positioned above the memory controller and electrically connected to the memory controller, and a packaging substrate located below the memory controller and electrically connected to the memory controller. The die area of the memory controller is greater than the sum of the horizontal cross-sectional area of the memory stack and the die area of the processor circuit. There is no interposer between the packaging substrate and the memory controller, and there is no TSV on each semiconductor die.

Inventors

• 통 호-밍
• 루 차오-춘

Assignees

• 엔디-에이치아이 테크놀로지스 랩 아이엔씨
• 에트론 테크놀로지, 아이엔씨.

Dates

Publication Date

20260512

Application Date

20250912

Priority Date

20250221

Claims (20)

1. In IC structure, A first memory stack, the first memory stack is It includes a plurality of semiconductor dies horizontally separated from each other, and Herein, each semiconductor die comprises an upper surface, a lower surface facing the upper surface, and four sidewalls including a first sidewall, a second sidewall, a third sidewall, and a fourth sidewall, wherein a plurality of edge pads are arranged along the first sidewall, and wherein the area of the lower surface or the upper surface of each semiconductor die is greater than the area of any sidewall: A logic die having a memory controller disposed below the first memory stack and electrically connected to the plurality of edge pads of each semiconductor die; A logic die having a processor circuit disposed on top of a logic die having the above-mentioned memory controller and electrically connected; It includes a packaging substrate electrically connected and disposed below a logic die having the above-mentioned memory controller, and The die area of the logic die having the memory controller is greater than the sum of the horizontal cross-sectional area of the first memory stack and the die area of the logic die having the processor circuit, and An IC structure having no interposer between the above-mentioned packaging substrate and the logic die having the above-mentioned memory controller, and no TSVs on each semiconductor die.
2. In Article 1, An upwardly extending thermal conductive layer disposed between two adjacent semiconductor dies; the thermal conductivity of the upwardly extending thermal conductive layer is higher than the thermal conductivity of Si or SiO2 ; and/or An IC structure further comprising a thermal conductive layer extending laterally that covers the second sidewall of each of the plurality of semiconductor dies and is thermally connected to the thermal conductive layer extending upwardly, wherein the thermal conductive layer extending laterally faces the first sidewall of the plurality of semiconductor dies, and the thermal conductivity of the thermal conductive layer extending laterally is higher than the thermal conductivity of Si or SiO2 .
3. In claim 2, the thermal conductive layer extending upward or the thermal conductive layer extending sideways comprises undoped polysilicon, large crystalline silicon, SiC, BN, AlN, W, or copper, in an IC structure.
4. An IC structure according to claim 1, wherein each semiconductor die comprises a DRAM die, and a plurality of edge pads of each DRAM die comprises about 128 to 5000 edge pads, and the pitch between two adjacent edge pads is between about 5 μm and about 100 μm.
5. In claim 4, the plurality of edge pads of each semiconductor die comprises a subset of data pads, and the logic die having the memory controller selects a predetermined data width from a subset of data pads of one semiconductor die, a part of the plurality of semiconductor dies, or all of the plurality of semiconductor dies.
6. In claim 5, the IC structure wherein the predetermined data width selected by the logic die having the memory controller is set by the mode register of each semiconductor die.
7. In claim 5, the logic die having the memory controller selects the predetermined data width from a subset of data pads of part or all of the plurality of semiconductor dies by means of a cross-bar circuit, IC structure.
8. In claim 5, the logic die having the memory controller selects the predetermined data width from a subset of data pads of one, part or all of the plurality of semiconductor dies by means of a plurality of SRAM arrays corresponding to each of the plurality of semiconductor dies, wherein each SRAM array temporarily stores the predetermined data width from the corresponding semiconductor die.
9. In claim 4, the logic die having the memory controller comprises a plurality of TSVs, an IC structure.
10. In claim 1, the IC structure further comprises a heat sink on top of a logic die having the processor circuit, wherein the upper surface of the heat sink is on the same plane as the upper surface of the first memory stack,
11. In Article 1, It further includes a second memory stack, and the second memory stack A plurality of semiconductor dies horizontally separated from one another, wherein each semiconductor die comprises an upper surface, a lower surface facing the upper surface, and four sidewalls having a first sidewall, a second sidewall, a third sidewall, and a fourth sidewall, wherein a plurality of edge pads are arranged along the first sidewall, and wherein the area of the lower surface or the upper surface of each semiconductor die is greater than the area of any sidewall: and It includes an upwardly extending thermal conductive layer located between two adjacent semiconductor dies; wherein the thermal conductivity of the upwardly extending thermal conductive layer is higher than the thermal conductivity of Si or SiO2 , and An IC structure in which the first memory stack and the second memory stack are horizontally spaced apart from the logic die having the processor circuit and arranged along one side of the logic die having the processor circuit.
12. In Article 1, It further includes a second memory stack, a third memory stack, and a fourth memory stack, each of which further includes a plurality of semiconductor dies and a thermal conductive layer extending upward. The plurality of semiconductor dies are horizontally separated from one another, wherein each semiconductor die comprises an upper surface, a lower surface facing the upper surface, and four side walls having a first side wall, a second side wall, a third side wall, and a fourth side wall, and a plurality of edge pads are arranged along the first side wall, wherein the area of the lower surface or the upper surface is larger than the area of any side wall, and The thermally conductive layer extending upward is located between two adjacent semiconductor dies; wherein the thermal conductivity of the thermally conductive layer extending upward is higher than the thermal conductivity of Si or SiO2 , and An IC structure in which the first memory stack, the second memory stack, the third memory stack, and the fourth memory stack are horizontally spaced apart from the logic die having the processor circuit and are each arranged along four sides of the logic die having the processor circuit.
13. In claim 1, each edge pad of each semiconductor die comprises an edge contact in a back-end-of-line (BEOL) region and a conductive via in a dielectric layer above the edge contact and on the upper surface, wherein the area of the conductive via is larger than the area of the edge contact, an IC structure.
14. An IC structure according to claim 1, wherein each edge pad of each semiconductor die comprises an edge contact in a back-end-of-line (BEOL) region and a conductive via in a redistribution layer (RDL) above the edge contact and on the upper surface, wherein the area of the conductive via is larger than the area of the edge contact.
15. In claim 14, the edge contact is electrically connected to a signal pad in the back-end-of-line (BEOL) region of the semiconductor die surrounded by a seal ring structure, in an IC structure.
16. An IC structure according to claim 1, wherein each edge pad of each semiconductor die comprises a conductive line in a redistribution layer (RDL), said conductive line is electrically connected to a signal pad in a back-end-of-line (BEOL) region of said semiconductor die surrounded by a seal ring structure.
17. In claim 16, the IC structure wherein the RDL comprises a plurality of stacked dielectric layers in which the conductive line is located internally.
18. An IC structure according to claim 17, wherein a portion of the conductive line is configured to be placed in the scribe line region of the semiconductor wafer before the semiconductor wafer is diced.
19. In IC structure, Memory stack, the above memory stack is It comprises a plurality of semiconductor dies horizontally separated from one another, wherein each semiconductor die comprises an upper surface, a lower surface facing the upper surface, and four sidewalls including a first sidewall, a second sidewall, a third sidewall, and a fourth sidewall, and a plurality of edge pads are arranged along the first sidewall, wherein the area of the lower surface or the upper surface of each semiconductor die is greater than the area of any sidewall: A logic die having a memory controller and a processor circuit disposed below the memory stack and electrically connected to the plurality of edge pads of each semiconductor die; and It includes a packaging substrate electrically connected to the lower part of a logic die having the above-mentioned memory controller and processor circuit, and An IC structure having no interposer between the above-mentioned packaging substrate and the logic die having the memory controller and processor circuit, and no TSVs on each semiconductor die.
20. In Article 19, An upwardly extending thermal conductive layer disposed between two adjacent semiconductor dies; the thermal conductivity of the upwardly extending thermal conductive layer is higher than the thermal conductivity of Si or SiO2 ; and/or An IC structure comprising a laterally extending thermal conductive layer covering the second sidewall of each of the plurality of semiconductor dies and thermally coupled to the thermally extending thermal conductive layer, wherein the laterally extending thermal conductive layer faces the first sidewall of the plurality of semiconductor dies, and the thermal conductivity of the laterally extending thermal conductive layer is higher than the thermal conductivity of Si or SiO2 .

Description

High Bandwidth Memory Stack with Side Edge Interconnection and 3D IC Structure Including the Same This application claims the benefit of U.S. Provisional Application No. 63/733,458 filed December 13, 2024, and is a partial continuation of U.S. Non-Application No. 18/471,670 filed September 21, 2023, which claims the benefit of U.S. Provisional Application No. 63/409,852 filed September 26, 2022, the disclosures of all of these are incorporated herein by reference in their entirety. The present disclosure generally relates to a memory stack within an IC structure, and more specifically to a high-bandwidth memory stack having lateral edge interconnects and a 3D IC structure including the same. 2.5D/3D ICs are recognized as next-generation semiconductor technologies that offer the advantages of high performance, low power consumption, small physical size, and high integration density. 2.5D/3D ICs provide a way to continuously meet the performance and cost requirements of next-generation devices while reducing process complexity and maintaining greater flexibility in gate length. Therefore, 2.5D/3D ICs are expected to provide wide applicability in High-Performance Computing (HPC) and data centers, Artificial Intelligence (AI)/Machine Learning (ML), 5G/6G networks, graphics, smartphones/wearables, automotive, and other applications requiring "extreme" ultra-high performance and high-power efficiency devices. Commercial 2.5D/3D ICs, such as 3D high-bandwidth memory (HBM) DRAM memory die stacks, are increasingly being used on logic, and these HBM devices include through silicon vias (TSVs) on both the active die and the silicon interposer. Additionally, 2.5D/3D ICs enable the vertical stacking of heterogeneous dies from different manufacturing processes and nodes, chip reuse, and system-in-a-package (SiP) chiplets for high-performance applications, which are already overcoming the limitations of a single die at state-of-the-art nodes. As illustrated in FIG. 1, a COWOS (chips-on-wafer-on-substrate) structure (20) comprises an HBM structure (21) having TSVs (201) (having a plurality of DRAM memory dies (211) and a controller (213), a logic die (22) (such as a GPU or SOC chip), a silicon interposer (23) having TSVs, and a packaging substrate (24), wherein the HBM structure (21) and the logic die (22) are stacked on the silicon interposer (23), and then the silicon interposer (23) is stacked on the packaging substrate (24). However, 2.5D/3D ICs adopt packaging topologies featuring upper and lower electrical interconnections created by the aforementioned interconnection technologies, such as microbumps, TSVs, and redistribution layers (RDLs). These upper and lower electrical interconnections impose severe constraints on PPAC (power, performance, area, and cost) optimization for 3D IC designers to derive optimal design solutions. In particular, there are difficulties in forming TSVs on semiconductor dies and aligning TSVs for each semiconductor die. Furthermore, as the monolithic integration capability of silicon chips grows from GSI (Gigascale Integration: billions of transistors on a die) to TSI (Terascale Integration: trillions of transistors on a die), the power consumption required to operate such a massive number of transistors is increasing rapidly. This negatively raises the transistor junction temperature and, consequently, the overall chip temperature due to current-limited heat dissipation capabilities (e.g., the thermal conductivity index of silicon dioxide/silicon is very low). Even worse, insufficient heat dissipation, which raises the chip operating temperature due to the stacking of multiple DRAM memory semiconductor dies (or HBM) in 2.5D/3D ICs, is considered the worst problem of HBM architecture. According to a first aspect of the present disclosure, an IC structure comprises a first memory stack, wherein the first memory stack comprises a plurality of semiconductor dies horizontally separated from one another, wherein each semiconductor die comprises an upper surface, a lower surface facing the upper surface, and four sidewalls including a first sidewall, a second sidewall, a third sidewall, and a fourth sidewall, and a plurality of edge pads are arranged along the first sidewall. The area of the lower surface or the upper surface of each semiconductor die is greater than the area of any sidewall. The IC structure comprises a logic die having a memory controller disposed below the first memory stack and electrically connected to the plurality of edge pads of each semiconductor die; a logic die having a processor circuit disposed above the logic die having the memory controller and electrically connected; and a packaging substrate electrically connected below the logic die having the memory controller. The die area of the logic die having the memory controller is greater than the sum of the horizontal cross-sectional area of the first memory stack and the die area of the logic die having the processor