KR-20260067308-A - COWOS IC STRUCTURE WITH EDGE-PAD SEMICONDUCTOR DIE

Abstract

The IC structure comprises a memory stack including a plurality of semiconductor dies horizontally separated from one another, a memory controller chip, an interposer, a logic processor chip, and a packaging substrate. Each semiconductor die includes an upper surface, a lower surface, and four sidewalls, and a plurality of edge pads are arranged along the first sidewalls. The memory controller chip is positioned below the plurality of edge pads of each semiconductor die and is electrically connected, and the first sidewall of each semiconductor die faces the memory controller chip. The interposer is positioned below the memory controller chip and is electrically connected. The logic processor chip is electrically connected to the memory controller chip. The packaging substrate is positioned below the interposer and is electrically connected.

Inventors

• 통 호-밍
• 루 샤오-춘

Assignees

• 엔디-에이치아이 테크놀로지스 랩 아이엔씨
• 에트론 테크놀로지, 아이엔씨.

Dates

Publication Date

20260512

Application Date

20250915

Priority Date

20250221

Claims (12)

1. In IC structure, Memory stack, memory stack is It comprises a plurality of semiconductor dies horizontally separated from one another, wherein each semiconductor die comprises an upper surface, a lower surface opposite to the upper surface, and four side walls including a first side wall, a second side wall, a third side wall, and a fourth side wall, and a plurality of edge pads arranged along the first side wall, and the area of the lower surface or the upper surface of each semiconductor die is larger than the area of any side wall; A memory controller chip located below a plurality of edge pads of each semiconductor die and electrically connected, the first sidewall of each semiconductor die facing the memory controller chip; An interposer located below the memory controller chip and electrically connected; A logic processor chip electrically connected to the memory controller chip; and An IC structure comprising a packaging substrate located below the above interposer and electrically connected.
2. In claim 1, the memory stack is A thermally conductive layer extending laterally to cover each second sidewall of the plurality of semiconductor dies; and/or It further includes an upwardly extending thermal conductive layer attached to the upper surface or lower surface of the first semiconductor die, and IC structure in which the thermal conductivity of the thermal conductive layer extending to the above side or the thermal conductive layer extending to the above upper side is higher than the thermal conductivity of Si or SiO2 .
3. In claim 2, the thermally conductive layer extending upward is thermally coupled with the thermally conductive layer extending sideways, and the thermally conductive layer extending upward or the thermally conductive layer extending sideways comprises SiC, BN, AlN, W, or copper, in an IC structure.
4. An IC structure according to claim 2, wherein the thermally conductive layer extending upward is disposed between the first semiconductor die and the second semiconductor die, or wherein the thermally conductive layer extending upward is located on the outermost sidewall of the memory stack.
5. In claim 1, each semiconductor die is a DRAM die and includes a data output between 128 and 2048 bits, an IC structure.
6. In claim 1, each edge pad of each semiconductor die is Edge contacts in the backend of line (BEOL) area; and An IC structure comprising a conductive via above the edge contact and within a dielectric layer or redistribution layer (RDL), wherein the area of the conductive via is larger than the area of the edge contact.
7. In claim 6, the edge contact is electrically connected to a signal pad in the BEOL region of the semiconductor die surrounded by a seal ring structure, in an IC structure.
8. An IC structure according to claim 1, wherein each edge pad of each semiconductor die includes a conductive line within a redistribution layer (RDL), and said conductive line is electrically connected to a signal pad in the back-end-of-line (BEOL) region of the semiconductor die surrounded by a seal ring structure.
9. In claim 8, the IC structure wherein the RDL comprises a plurality of stacked dielectric layers on which the conductive line is located.
10. An IC structure according to claim 9, wherein a portion of the conductive line is configured to be placed in a scribe line region (SL) of the semiconductor wafer before dicing the semiconductor wafer.
11. An IC structure according to claim 1, wherein the logic processor chip is disposed on the interposer, a heat sink is placed on the logic processor chip, and the upper surface of the heat sink is located substantially in the same plane as the upper surface of the memory stack.
12. In claim 1, the memory stack further comprises an upwardly extending thermal conductive layer covering each third sidewall of the plurality of semiconductor dies, wherein the upwardly extending thermal conductive layer is thermally coupled with a side-extending thermal conductive layer above each second sidewall of the plurality of semiconductor dies, and the thermal conductivity of the upwardly extending thermal conductive layer is higher than the thermal conductivity of Si or SiO2 , IC structure.

Description

COWOS IC structure with edge-pad semiconductor die This application claims the benefit of U.S. Provisional Application No. 63/730,072 filed December 10, 2024, and is a partial continuation of U.S. Non-Application No. 18/471,670 filed September 21, 2023, which claims the benefit of U.S. Provisional Application No. 63/409,852 filed September 26, 2022, and all disclosures of these applications are incorporated herein by reference in their entirety. The present disclosure generally relates to a COWOS IC structure, and more specifically to a COWOS IC structure having an edge pad semiconductor die. 2.5D/3D ICs are recognized as next-generation semiconductor technologies that offer the advantages of high performance, low power consumption, small physical size, and high integration density. 2.5D/3D ICs provide a way to continuously meet the performance and cost requirements of next-generation devices while reducing process complexity and maintaining greater flexibility in gate length. Therefore, 2.5D/3D ICs are expected to provide wide applicability in High-Performance Computing (HPC) and data centers, Artificial Intelligence (AI)/Machine Learning (ML), 5G/6G networks, graphics, smartphones/wearables, automotive, and other applications requiring "extreme" ultra-high performance and high-power efficiency devices. Commercial 2.5D/3D ICs, such as 3D high-bandwidth memory (HBM) DRAM memory die stacks, are increasingly being used on logic, and these HBM devices include through silicon vias (TSVs) on both the active die and the silicon interposer. Additionally, 2.5D/3D ICs enable the vertical stacking of heterogeneous dies from different manufacturing processes and nodes, chip reuse, and system-in-a-package (SiP) chiplets for high-performance applications, which are already overcoming the limitations of a single die at state-of-the-art nodes. As illustrated in FIG. 1, a COWOS (chips-on-wafer-on-substrate) structure (20) comprises an HBM structure (21) having TSVs (201) (having a plurality of DRAM memory dies (211) and a controller (213), a logic die (22) (such as a GPU or SOC chip), a silicon interposer (23) having TSVs, and a packaging substrate (24), wherein the HBM structure (21) and the logic die (22) are stacked on the silicon interposer (23), and then the silicon interposer (23) is stacked on the packaging substrate (24). However, 2.5D/3D ICs adopt packaging topologies featuring upper and lower electrical interconnections created by the aforementioned interconnection technologies, such as microbumps, TSVs, and redistribution layers (RDLs). These upper and lower electrical interconnections impose severe constraints on PPAC (power, performance, area, and cost) optimization for 3D IC designers to derive optimal design solutions. In particular, there are difficulties in forming TSVs on semiconductor dies and aligning TSVs for each semiconductor die. Furthermore, as the monolithic integration capability of silicon chips grows from GSI (Gigascale Integration: billions of transistors on a die) to TSI (Terascale Integration: trillions of transistors on a die), the power consumption required to operate such a massive number of transistors is increasing rapidly. This negatively raises the transistor junction temperature and, consequently, the overall chip temperature due to current-limited heat dissipation capabilities (e.g., the thermal conductivity index of silicon dioxide/silicon is very low). Even worse, insufficient heat dissipation, which raises the chip operating temperature due to the stacking of multiple DRAM memory semiconductor dies (or HBM) in 2.5D/3D ICs, is considered the worst problem of HBM architecture. According to a first aspect of the present disclosure, an IC structure comprises a memory stack, a memory controller chip, an interposer, a logic processor chip, and a packaging substrate. The memory stack comprises a plurality of semiconductor dies. The plurality of semiconductor dies are horizontally separated from one another, and each semiconductor die comprises an upper surface, a lower surface opposite to the upper surface, and four sidewalls including a first sidewall, a second sidewall, a third sidewall, and a fourth sidewall, and a plurality of edge pads arranged along the first sidewall, wherein the area of the lower surface or the upper surface of each semiconductor die is larger than the area of any sidewall. A memory controller chip is located below and electrically connected to the plurality of edge pads of each semiconductor die, and the first sidewall of each semiconductor die faces the memory controller chip. An interposer is located below and electrically connected to the memory controller chip. A logic processor chip is electrically connected to the memory controller chip. A packaging substrate is located below and electrically connected to the interposer. According to some embodiments of the present disclosure, the memory stack comprises a thermally conductive layer extending upward and/or