KR-20260067312-A - INTEGRATED CIRCUIT DEVICES INCLUDING HIGH-DENSITY CAPACITORS

Abstract

An integrated circuit device comprises a substrate and a metal-oxide-semiconductor capacitor (MOSCAP) disposed on the substrate. The MOSCAP comprises a lower semiconductor device disposed on the substrate and an upper semiconductor device disposed on the lower semiconductor device, wherein the lower semiconductor device comprises a pair of lower source/drain regions and a lower gate structure disposed between the pair of lower source/drain regions, and the upper semiconductor device comprises a pair of upper source/drain regions and an upper gate structure disposed between the pair of upper source/drain regions. The lower gate structure is electrically connected to both of the pair of upper source/drain regions.

Inventors

• 신효종
• 박영국
• 서강일
• 신종민
• 박범진

Assignees

• 삼성전자주식회사

Dates

Publication Date

20260512

Application Date

20250926

Priority Date

20250613

Claims (20)

1. An integrated circuit device comprising a substrate and a metal-oxide-semiconductor capacitor (MOSCAP) disposed on the substrate, The above MOSCAP includes a lower semiconductor device disposed on the substrate and an upper semiconductor device disposed on the lower semiconductor device, and The lower semiconductor device includes a pair of lower source/drain regions and a lower gate structure disposed between the pair of lower source/drain regions, and The upper semiconductor device includes a pair of upper source/drain regions and an upper gate structure disposed between the pair of upper source/drain regions, and The above lower gate structure is electrically connected to both of the above pair of upper source/drain regions, Integrated circuit device.
2. In paragraph 1, An integrated circuit device characterized in that the upper gate structure is electrically connected to both of the pair of lower source/drain regions.
3. In paragraph 1, The above MOSCAP further includes an insulating region located between the lower gate structure and the upper gate structure, and An integrated circuit device characterized in that the lower gate structure is electrically isolated from the upper gate structure by the insulating region.
4. In paragraph 1, The above lower gate structure is configured to receive a first voltage, and An integrated circuit device characterized in that the upper gate structure is configured to receive a second voltage different from the first voltage.
5. In paragraph 1, The lower semiconductor device further includes lower channel layers disposed between the pair of lower source/drain regions, and the lower channel layers are spaced apart from each other in a direction perpendicular to the upper surface of the substrate. An integrated circuit device characterized in that the upper semiconductor device further comprises upper channel layers disposed between the pair of upper source/drain regions, and the upper channel layers are spaced apart from each other in the vertical direction.
6. In paragraph 1, The above pair of lower source/drain regions has a first conductivity type, and An integrated circuit device characterized in that the above pair of upper source/drain regions have a second conductivity type different from the first conductivity type.
7. In paragraph 1, The lower gate structure and the upper gate structure are each configured to receive a first voltage and a second voltage, and An integrated circuit device characterized in that the above MOSCAP is configured to have a maximum capacitance value when both the lower semiconductor device and the upper semiconductor device operate in the inversion region by the first voltage and the second voltage.
8. Substrate; A front metal-oxide-metal capacitor (MOMCAP) disposed on a first surface of the substrate; and A rear MOMCAP disposed on a second surface of the substrate facing the first surface and electrically connected to the front MOMCAP, comprising Integrated circuit device.
9. In paragraph 8, The above rear MOMCAP includes an upper rear metallization pattern comprising interdigitated upper rear fingers, and An integrated circuit device characterized in that the above-mentioned interlocked upper rear fingers extend in a first direction parallel to the first surface of the substrate and are spaced apart from each other in a second direction intersecting the first direction.
10. In Paragraph 9, It further includes a semiconductor element disposed on the first surface of the substrate, and The above semiconductor device includes a pair of source/drain regions and a gate structure disposed between them, and An integrated circuit device characterized in that the gate structure extends in the second direction, and the gate structure overlaps with at least one of the engaged upper rear fingers in a third direction perpendicular to the first surface of the substrate.
11. In Paragraph 9, The upper rear metallization pattern comprises a first upper rear metallization layer including first fingers among the interlocked upper rear fingers, and a second upper rear metallization layer including second fingers among the interlocked upper rear fingers. The first upper rear metallization layer is capacitively coupled with the second upper rear metallization layer, and An integrated circuit device characterized in that the above rear MOMCAP further includes an insulating layer between the first upper rear metallization layer and the second upper rear metallization layer.
12. In Paragraph 9, The above rear MOMCAP further includes a lower rear metallization pattern disposed on the lower surface of the above upper rear metallization pattern, and The above lower rear metallized pattern includes interlocked lower rear fingers, and An integrated circuit device characterized in that the interlocked lower rear fingers extend in the second direction and are spaced apart from each other in the first direction.
13. In Paragraph 12, The above rear MOMCAP further includes a rear insulating layer disposed between the lower rear metallization pattern and the upper rear metallization pattern in a third direction perpendicular to the first surface of the substrate, and An integrated circuit device characterized in that at least one of the above-mentioned interlocked upper rear fingers overlaps with at least one of the above-mentioned interlocked lower rear fingers in the above-mentioned third direction.
14. In paragraph 8, It further includes a metal-oxide-semiconductor capacitor (MOSCAP) disposed between the front MOMCAP and the rear MOMCAP, and The above MOSCAP includes a lower semiconductor device disposed on the substrate and an upper semiconductor device disposed on the lower semiconductor device, and The above-mentioned lower semiconductor device includes a pair of lower source/drain regions and a lower gate structure between them, and An integrated circuit device characterized in that the upper semiconductor device comprises a pair of upper source/drain regions and an upper gate structure between them.
15. In Paragraph 14, It further includes an upper source/drain contact structure extending between the front MOMCAP and the rear MOMCAP, and An integrated circuit device characterized in that the first region of the above pair of upper source/drain regions is electrically connected to both the front MOMCAP and the rear MOMCAP through the upper source/drain contact structure.
16. In Paragraph 14, It further includes a lower source/drain contact structure extending between the front MOMCAP and the rear MOMCAP, and An integrated circuit device characterized in that the first region of the above pair of lower source/drain regions is electrically connected to both the front MOMCAP and the rear MOMCAP through the lower source/drain contact structure.
17. Substrate; A metal-oxide-semiconductor capacitor (MOSCAP) disposed on a first surface of the substrate; and A rear metal-oxide-metal capacitor (MOMCAP) disposed on a second surface of the substrate facing the first surface and electrically connected to the MOSCAP; comprising Integrated circuit device.
18. In Paragraph 17, The above MOSCAP includes a lower semiconductor device disposed on the substrate and an upper semiconductor device disposed on the lower semiconductor device, and The above-mentioned lower semiconductor device includes a pair of lower source/drain regions and a lower gate structure between them, and An integrated circuit device characterized in that the upper semiconductor device comprises a pair of upper source/drain regions and an upper gate structure between them.
19. In Paragraph 18, It further includes a lower gate contact extending into the substrate, and An integrated circuit device characterized in that the lower gate structure is electrically connected to the rear MOMCAP through the lower gate contact.
20. In Paragraph 18, It further includes a lower source/drain contact structure extending into the substrate, and An integrated circuit device characterized in that the first region of the above pair of lower source/drain regions is electrically connected to the rear MOMCAP through the lower source/drain contact structure.

Description

Integrated circuit devices including high-density capacitors The technical field of the present invention relates to an integrated circuit device, and more specifically, to an integrated circuit device including a highly integrated capacitor. In integrated circuit (IC) devices, the size of transistors has been continuously reduced to miniaturize logic devices. As a result, gate-all-around (GAA) structures (e.g., multi-bridge channel field-effect transistors (MBCFET™) and nanosheet FETs (NSFETs)) have been developed. Furthermore, as technologies for increasing transistor density continue to advance, three-dimensional (3D) device structures, such as stacked transistors, are being considered. A stacked transistor (or transistor stack) may include a first transistor and a second transistor. The first transistor may be a first type of transistor (e.g., an n-type metal-oxide-semiconductor (nMOS) transistor), and the second transistor may be a second type of transistor (e.g., a p-type metal-oxide-semiconductor (pMOS) transistor). The first and second types of transistors may be complementary to each other and thus may be part of a complementary metal-oxide-semiconductor (CMOS) structure. The first and second transistors can be stacked in any order (e.g., the first transistor is on top or the second transistor is on top), thereby forming a stack including an upper transistor and a lower transistor. Figure 1 is a schematic cross-sectional view of a typical integrated circuit device. FIG. 2a is a schematic block diagram of a transistor stack of an integrated circuit device according to some embodiments. FIG. 2b is a schematic plan view of an integrated circuit device according to some embodiments. FIG. 2c is a schematic cross-sectional view along the line AA' of FIG. 2b. FIG. 2d is a schematic cross-sectional view along the line BB' of FIG. 2b. FIG. 3a is a schematic block diagram of a MOSCAP of an integrated circuit device according to some embodiments. FIG. 3b is a schematic plan view of an integrated circuit device according to some embodiments. FIG. 3c is a schematic cross-sectional view along the BB' line of FIG. 3b. FIG. 3d is a schematic cross-sectional view along the CC' line of FIG. 3b. FIG. 3e is a schematic cross-sectional view along the DD' line of FIG. 3b. FIG. 3f is a schematic plan view of a front MOMCAP according to some embodiments. FIG. 3g is a schematic plan view of an integrated circuit device including the front MOMCAP of FIG. 3f according to some embodiment. FIG. 3h is a schematic plan view of a rear MOMCAP according to some embodiments. FIG. 3i is a schematic plan view of an integrated circuit device including a rear MOMCAP of FIG. 3h according to some embodiment. FIG. 3j is a schematic circuit diagram of the MOSCAP of FIG. 3a, FIG. 3b, FIG. 3c, FIG. 3d, and FIG. 3e according to some embodiments. FIG. 3k is a schematic circuit diagram of the integrated circuit device of FIG. 3a, FIG. 3b, FIG. 3c, FIG. 3d, and FIG. 3e according to some embodiments. FIG. 4 is a graph showing the CV curves of the MOSCAPs of FIG. 3a, 3b, 3c, 3d, and 3e according to some embodiments. FIG. 5a is a schematic plan view of a front MOMCAP according to an additional embodiment. FIG. 5b is a schematic plan view of a rear MOMCAP according to an additional embodiment. FIG. 6a is a schematic cross-sectional view along the CC' line of FIG. 3b according to an additional embodiment. FIG. 6b is a schematic cross-sectional view along the line DD' of FIG. 3b according to an additional embodiment. According to exemplary embodiments of this specification, an integrated circuit device comprising a highly integrated capacitor is provided. The embodiments of this application are partly derived from the recognition that it may be advantageous to provide one or more highly integrated capacitors in the integrated circuit device by modifying the existing architecture used to form a three-dimensional (3D) stacked transistor (e.g., a 3D stacked field-effect transistor (3DSFET)) within the integrated circuit device. For example, such capacitors may function as decoupling capacitors that contribute to providing a stable voltage supply and/or removing noise within the integrated circuit device, but are not limited thereto. By modifying the existing 3D stacked transistor architecture, the capacitors can be seamlessly implemented in the integrated circuit device while operating with the 3D stacked transistor. The embodiments will be described in more detail below with reference to the attached drawings. Figure 1 is a schematic cross-sectional view of a typical integrated circuit device. Referring to FIG. 1, a general integrated circuit device (1) may include a substrate (10), a planar transistor (2) on the substrate (10), and a metal-oxide-semiconductor capacitor (MOSCAP) (3) on the substrate (10). For example, as shown in FIG. 1, the planar transistor (2) may be a metal-oxide-semiconductor field-effect transistor (MOSFET), but the present disclos