KR-20260067319-A - METHOD AND APPARATUS FOR LOW DENSITY PARITY CHECK DECODING

Abstract

A method of a first communication node according to one embodiment of the present disclosure may include: obtaining channel LLR (log-likelihood ratio) values based on a signal received from a second communication node; generating first data based on the LLR values and storing the first data in a posteriori probability (APP) memory; performing column rearrangement on the first data stored in the APP memory and selecting a second data from the column-rearranged first data; generating third data by aligning the second data through odd and even scheduling; generating fourth data by performing a variable node processing (VNP), a check node processing (CNP), and an APP update process on the third data; and storing the fourth data in the APP memory.

Inventors

• 최정원
• 김남일
• 김재화
• 이영주

Assignees

• 한국전자통신연구원

Dates

Publication Date

20260512

Application Date

20251024

Priority Date

20241105

Claims (1)

1. As a method of the first communication node, A step of obtaining channel LLR (log-likelihood ratio) values based on a signal received from a second communication node; A step of generating first data based on the above LLR values and storing the first data in an APP (a posteriori probability) memory; A step of performing column rearrangement on the first data stored in the APP memory and selecting second data from the column-rearranged first data; A step of generating third data by aligning the second data through odd and even scheduling; A step of generating fourth data by performing a VNP (variable node processing), a CNP (check node processing), and an APP update process on the third data; and A step comprising storing the above-mentioned fourth data in the above-mentioned APP memory, Method of the first communication node.

Description

Method and apparatus for low-density parity check decoding The present disclosure relates to communication technology, and more specifically, to technology for implementing a low-density-based parity check decoder in a communication system. Along with the advancement of information and communication technology, various wireless communication technologies are being developed. Representative wireless communication technologies include LTE (long term evolution) and NR (new radio), which are defined in the 3GPP (3rd generation partnership project) standards. LTE can be one of the wireless communication technologies among 4G (4th Generation) wireless communication technologies, and NR can be one of the wireless communication technologies among 5G (5th Generation) wireless communication technologies. To handle the surge in wireless data following the commercialization of 4G communication systems (e.g., communication systems supporting LTE), 5G communication systems (e.g., communication systems supporting NR) that use frequency bands higher than the frequency bands of 4G communication systems (e.g., frequency bands below 6 GHz) are being considered. 5G communication systems can support eMBB (enhanced Mobile BroadBand), URLLC (Ultra-Reliable and Low Latency Communication), and mMTC (massive Machine Type Communication). Recently, high-capacity packet transmission and low-latency, high-reliability communication may be required in wireless communication technology. Packet errors caused by channel noise and other interference can degrade the overall communication system capacity. Considering the characteristics of low-density parity check (LDPC) codes, such as high throughput, low latency, low decoding complexity, and various coding speeds, LDPC codes are defined as a channel coding technique for shared channels in 5G communication systems. Meanwhile, high-speed data transmission may require a high code rate. LDPC codes can perform better in high-code-rate environments than other channel codes, and parallel processing can be utilized in the hardware implementation of the decoding algorithm. LDPC codes can achieve excellent performance approaching channel capacity when using a decoding algorithm based on iterative decoding. While parallel processing of LDPC codes can increase the processing speed of the decoder, it can also increase computational complexity and hardware complexity. FIG. 1 is a conceptual diagram illustrating embodiments of a communication system. FIG. 2 is a block diagram illustrating embodiments of communication nodes constituting a communication system. Figure 3 is a block diagram illustrating a parity check matrix used in a 50-gigabit passive optical network. Figure 4 is a conceptual diagram illustrating a decoder structure with partial parallelization applied. Figure 5a is a block diagram illustrating the structure of a decoder according to a basic reading permutation process. FIG. 5b is a block diagram illustrating a decoder structure with a column rearrangement method applied according to embodiments. Figure 6a is a conceptual diagram illustrating a read cycle process with odd and even scheduling applied. Figure 6b is a conceptual diagram illustrating a read cycle process with odd and even scheduling applied. Figure 7a is a graph comparing MUX network usage during the read permutation process. Figure 7b is a graph comparing MUX network usage during the read cycle. Figure 8 is a graph comparing the error correction performance of LDPC decoders. FIG. 9 is a flowchart illustrating the decoding process of a communication node according to embodiments. The present disclosure is capable of various modifications and may have various embodiments, and specific embodiments are illustrated in the drawings and described in detail. However, this is not intended to limit the present disclosure to specific embodiments, and it should be understood that it includes all modifications, equivalents, and substitutions that fall within the spirit and scope of the present disclosure. Terms such as "first," "second," etc., may be used to describe various components, but said components should not be limited by said terms. Such terms are used solely for the purpose of distinguishing one component from another. For example, without departing from the scope of the present disclosure, the first component may be named the second component, and similarly, the second component may be named the first component. The term "and/or" includes a combination of a plurality of related described items or any of a plurality of related described items. When it is stated that one component is "connected" or "connected" to another component, it should be understood that while it may be directly connected or connected to that other component, there may also be other components in between. On the other hand, when it is stated that one component is "directly connected" or "directly connected" to another component, it should be understood that t