KR-20260067344-A - Growth substrate wafer for high-performance GaN switching power devices, epitaxy wafer using the same, and manufacturing method thereof

KR20260067344AKR 20260067344 AKR20260067344 AKR 20260067344AKR-20260067344-A

Abstract

Embodiments according to the present invention provide a growth substrate wafer for a high-performance GaN switching power device, comprising: a Si (111) growth substrate; a first AlN nucleation layer formed on the Si (111) growth substrate; and a plurality of SiOx protrusions arranged discontinuously spaced apart on the first AlN nucleation layer, wherein the surface of the first AlN nucleation layer is exposed in the region between the plurality of SiOx protrusions.

Inventors

송준오
문지형
한영훈
윤형선

Assignees

웨이브로드 주식회사

Dates

Publication Date: 20260512
Application Date: 20251104
Priority Date: 20241105

Claims (11)

Si(111) growth substrate; A first AlN nucleation layer formed on the above Si (111) growth substrate; and It includes a plurality of SiOx protrusions arranged discontinuously spaced apart on the first AlN nucleation layer, A growth substrate wafer for a high-performance GaN switching power device, characterized in that the surface of the first AlN nucleation layer is exposed in the region between the plurality of SiOx protrusions.
In claim 1, A growth substrate wafer for a high-performance GaN switching power device, characterized in that the shape of the SiOx protrusions is a lens, truncated, dome, cone, polygon, or cubic shape.
In claim 1, A growth substrate wafer for a high-performance GaN switching power device, further comprising a SiNx protective film (25) formed between the first AlN nucleation layer and the plurality of SiOx protrusions.
A growth substrate wafer according to any one of claims 1 to 3; A GaN-based composite growth layer grown from the surface of the first AlN nucleation layer exposed between the plurality of SiOx protrusions, covering the upper portion of the SiOx protrusions and merged with each other; and An epitaxy wafer using a growth substrate wafer for a high-performance GaN switching power device, characterized by including a GaN HEMT (High Electron Mobility Transistor) device active layer formed on the above GaN-based composite growth layer.
In claim 4, An epitaxial wafer using a growth substrate wafer for a high-performance GaN switching power device, characterized in that the above GaN-based composite growth layer is an undoped GaN (uGaN) single layer.
In claim 4, An epitaxy wafer using a growth substrate wafer for a high-performance GaN switching power device, characterized in that the above GaN-based composite growth layer has a multilayer structure in which uGaN layers and AlN layers or AlGaN layers are alternately stacked.
In claim 4, An epitaxial wafer using a growth substrate wafer for a high-performance GaN switching power device, characterized by further including an Al(z)Ga(1-z)N stress control layer formed between the above GaN-based composite growth layer and the above GaN HEMT device active layer.
In claim 4, An epitaxy wafer using a growth substrate wafer for a high-performance GaN switching power device, characterized by further including a second AlN nucleation layer formed between the plurality of SiOx protrusions and the GaN-based composite growth layer, and covering the surface of the exposed first AlN nucleation layer and the surface of the SiOx protrusions.
(a) A step of preparing a Si(111) growth substrate; (b) a step of forming a first AlN nucleation layer on the above Si (111) growth substrate; (c) a step of depositing a SiOx thin film on the first AlN nucleation layer; (d) patterning the above SiOx thin film to form a plurality of discontinuously spaced SiOx protrusions; (e) a step of forming a GaN-based composite growth layer by growing a GaN-based material laterally (Epitaxial Lateral Overgrowth, ELOG) from the first AlN nucleation layer exposed between the SiOx protrusions and integrating it on the SiOx protrusions; and (f) A method for manufacturing an epitaxial wafer using a growth substrate wafer for a high-performance GaN switching power device, characterized by including the step of stacking a GaN HEMT (High Electron Mobility Transistor) device active layer on the above GaN-based composite growth layer.
In claim 9, The above step (e) is a method for manufacturing an epitaxial wafer using a growth substrate wafer for a high-performance GaN switching power device, characterized by alternately growing a uGaN layer and an AlN layer or an AlGaN layer to form the GaN-based composite growth layer.
In claim 9, A method for manufacturing an epitaxy wafer using a growth substrate wafer for a high-performance GaN switching power device, characterized by further including the step of forming a second AlN nucleation layer on the first AlN nucleation layer and the plurality of SiOx protrusions between the above steps (d) and (e).

Description

Growth substrate wafer for high-performance GaN switching power devices, epitaxy wafer using the same, and manufacturing method thereof The present invention relates to a high-performance switching power device using gallium nitride (GaN), and more specifically to a patterned silicon substrate (PSiS, Patterned Si Substrate) for forming a high-quality GaN epitaxial layer on a silicon (Si) growth substrate, an epitaxial wafer that significantly reduces threading dislocation density (TDD) using said substrate, and a method for manufacturing said. Gallium nitride (GaN) compound semiconductors are wide-bandgap materials that possess a higher breakdown electric field, superior thermal conductivity, and high carrier mobility than conventional semiconductor materials such as silicon (Si) and gallium arsenide (GaAs). Thanks to these characteristics, they enable the realization of high power density in smaller sizes, making them a key material for next-generation power semiconductor devices. For GaN power semiconductors to be competitive in the market, Normally-OFF operation with high cutoff voltage and low leakage current is essential. The most ideal structure to achieve this is a vertical FET with a thick epitaxial region, but because commercialization of GaN-on-GaN substrates is difficult and the efficiency of the ion implantation process is low, High Electron Mobility Transistors (HEMTs) with a horizontal structure, which grow thin films on heterogeneous substrates, are currently being fabricated. At this time, heterogeneous growth substrates such as sapphire, silicon (Si), and silicon carbide (SiC) are used, but due to the mismatch in lattice constants and thermal expansion coefficients between the GaN epitaxial layer and the growth substrate, a very high real dislocation density (TDD) of 10⁷ to 10¹⁰ / cm² occurs. These threading dislocations are a chronic problem that has a critical adverse effect on device performance and reliability. Specifically, threading dislocations cause various problems as follows. (1) Increase in leakage current: Screw and mixed dislocations containing screw components act as the main leakage path, degrading the off-state characteristics of the device. (2) Decrease in Blocking Voltage: The actual potential acts as a 'hot spot' that causes electric field crowding at a specific point within the device, which causes premature breakdown before the device reaches its original breakdown voltage. (3) Reduction in switching frequency: The real potential acts as a center for scattering and trapping in the electron's path of movement, thereby reducing carrier mobility. This performance degradation is particularly pronounced in horizontal HEMT structures where current flows transversely to the real potential. (4) Increase in Dynamic On-resistance (R ON ): During high-voltage switching operation, charges are trapped in faults including real potential and then gradually released, causing a temporary increase in on-resistance immediately after the switch is turned on. This is a major cause of increased power loss. (5) Degradation of reliability: Crystal defects such as real potentials become the starting point for various degradation mechanisms, such as gate edge degradation, hot electron generation, and thin film separation, when the device operates in a high electric field and temperature environment, thereby shortening the device's lifespan. Therefore, in order to commercialize high-performance, high-reliability GaN power devices, there is an urgent need to develop high-quality epitaxial growth technology capable of controlling TDD to less than 10⁸ /cm² on large-diameter Si substrates of 8 inches or 12 inches. FIG. 1 is a diagram showing the structure of a PSiS growth substrate wafer according to one embodiment of the present invention. FIG. 2 is a drawing showing a modified example of FIG. 1. FIG. 3 is a diagram showing a structure in which a GaN-based composite growth layer is formed using the PSiS growth substrate wafer of FIG. 1. FIG. 4 is a drawing showing an epitaxial wafer having a HEMT structure stacked on the GaN-based composite growth layer of FIG. 3. FIGS. 5 and FIGS. 6 are drawings showing variations of FIGS. 3. Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms, and these embodiments are provided merely to ensure that the disclosure of the present invention is complete and to fully inform a person skilled in the art of the scope of the invention. The present invention includes several technical configurations organically combined to effectively control threading dislocations, a chronic problem in GaN-on-Si technology. First, referring to FIGS 1 and FIGS 2, the PSiS (Patterned Si Substrate) growth substrate, which is the core of the present invention, has technical significance i