KR-20260067355-A - Display panel

Abstract

The present application discloses a display panel, wherein the gate driving unit of the display panel comprises an output circuit, a receiving circuit, and a storage capacitor connected to each other, and both the output circuit and the receiving circuit comprise a gate transistor, and the active portion of at least one gate transistor is located in a first active layer, and one electrode plate of the storage capacitor is located in a second active layer, and the gate of the gate transistor and the other electrode plate of the storage capacitor are located in a first gate layer, and the first gate layer, the first active layer, and the second active layer are all disposed on different layers.

Inventors

• 장 유헹
• 리우 항

Assignees

• 우한 차이나 스타 옵토일렉트로닉스 세미컨덕터 디스플레이 테크놀로지 컴퍼니 리미티드

Dates

Publication Date

20260512

Application Date

20241115

Priority Date

20241104

Claims (20)

1. A display panel comprising a plurality of gate driving units, wherein the gate driving units include an output circuit, a receiving circuit, and a storage capacitor connected to each other, and the output circuit and the receiving circuit both include gate transistors, and the area of the gate transistor of the output circuit is larger than the area of the gate transistor of the receiving circuit. Here, at least one active portion of the gate transistor is located in a first active layer, one electrode plate of the storage capacitor is located in a second active layer, the gate of the gate transistor and the other electrode plate of the storage capacitor are located in a first gate layer, and the first gate layer, the first active layer, and the second active layer are all disposed on different layers in a display panel.
2. In paragraph 1, The output circuit includes a first output transistor, and the receiving circuit includes a first node control module, and the first output transistor and the first node control module are connected to a first node, and Here, the storage capacitor includes a first capacitor, the first capacitor includes a first electrode plate and a second electrode plate, the first electrode plate and the second electrode plate are each connected to different internal nodes of the first node control module, the first electrode plate is located in the second active layer, and the second electrode plate is located in the first gate layer, forming a display panel.
3. In paragraph 2, The output circuit includes a second output transistor connected to the first output transistor, and the receiving circuit includes a second node control module, and the second output transistor and the second node control module are connected to a second node. Here, the storage capacitor includes a second capacitor, the second capacitor includes a third electrode plate and a fourth electrode plate, the third electrode plate and the fourth electrode plate are each connected to different internal nodes of the second node control module, the third electrode plate is located in the second active layer, and the fourth electrode plate is located in the first gate layer, forming a display panel.
4. In paragraph 3, A display panel in which the overlapping area of the first electrode plate and the second electrode plate is larger than the overlapping area of the third electrode plate and the fourth electrode plate.
5. In paragraph 3, The above storage capacitor further includes a third capacitor, and the third capacitor includes a fifth electrode plate and a sixth electrode plate, wherein the fifth electrode plate is located in the second active layer and the sixth electrode plate is located in the first gate layer. Here, the sixth electrode plate is connected to the source of the second output transistor, and the fifth electrode plate is connected to the second node, forming a display panel.
6. In paragraph 5, The first gate layer includes a first gate of the first output transistor and a second gate of the second output transistor, and the first gate and the second gate are arranged in a first direction. Here, the area of the first gate is smaller than the area of the second gate of the display panel.
7. In paragraph 6, The first gate comprises a first trunk gate and a plurality of first branch gates connected to the first trunk gate, the first trunk gate extends along the first direction, the plurality of first branch gates extend along the second direction, and the plurality of first branch gates are spaced apart in the first direction. The second gate comprises a second trunk gate and a plurality of second branch gates connected to the second trunk gate, the second trunk gate extends along the first direction, the plurality of second branch gates extend along the second direction, and the plurality of second branch gates are spaced apart in the first direction. Here, a portion of the second trunk gate and the second branch gate is multiplexed into the sixth electrode plate, the second direction is parallel to the scan line of the display panel, and the angle formed by the first direction and the second direction is greater than 0° and less than or equal to 90°, for a display panel.
8. In Paragraph 7, A display panel in the second direction where the line width of the first trunk gate is smaller than the line width of the second trunk gate.
9. In Paragraph 7, A display panel in which the length of the first branch gate in the second direction is shorter than the length of the second branch gate.
10. In Paragraph 7, The first gate layer further includes a second electrode plate of the first capacitor and a fourth electrode plate of the second capacitor, wherein the second electrode plate and the fourth electrode plate are arranged in the first direction, and the fourth electrode plate and the sixth electrode plate are arranged in the second direction. Here, the second electrode plate is a display panel that extends in the second direction and is connected to the first trunk gate.
11. In Paragraph 10, The second active layer comprises a first electrode plate of the first capacitor, a third electrode plate of the second capacitor, and a fifth electrode plate of the third capacitor, and A display panel in which, here, a portion of the outer contour of the first electrode plate extends outward relative to the outer contour of the second electrode plate, a portion of the outer contour of the third electrode plate extends outward relative to the outer contour of the fourth electrode plate, and a portion of the outer contour of the fifth electrode plate extends outward relative to the outer contour of the sixth electrode plate.
12. In Paragraph 7, The above display panel further includes a first source-drain layer disposed on the side of the second active layer far from the first active layer, and the first source-drain layer includes a first source and a first drain of the first output transistor, and The first drain comprises a plurality of first branch drains, and the first source comprises a plurality of first branch sources, and the plurality of first branch drains and the plurality of first branch sources all extend along the second direction, and the plurality of first branch drains and the plurality of first branch sources are spaced apart in the first direction. Here, each of the first branch gates is a display panel in which one of the first branch drains and one of the first branch sources are disposed on both sides of the first direction.
13. In Paragraph 12, The first source-drain layer further includes a second source and a second drain of the second output transistor, and The second drain comprises a plurality of second branch drains, and the second source comprises a plurality of second branch sources, wherein the plurality of second branch drains and the plurality of second branch drains all extend along the second direction, and the plurality of second branch drains and the plurality of second branch sources are spaced apart in the first direction, and each of the second branch gates has one second branch drain and one second branch source disposed on both sides of the first direction, and Herein, the first source drain layer further comprises a drain trunk extending along the first direction, a plurality of the second branch drains are connected to the drain trunk, and a plurality of the second branch sources, a plurality of the first branch drains, and a plurality of the first branch sources are arranged separately from the drain trunk in a display panel.
14. In Paragraph 13, The above display panel further includes a second gate layer disposed between the second active layer and the first source drain layer, and the second gate layer includes an output wiring extending along the first direction, and Here, a display panel electrically connected to the output wiring through a via hole, at one end of the receiving circuit of a plurality of the first branch sources and a plurality of the second branch sources.
15. In Paragraph 14, A display panel in which a plurality of the second branch drains and a plurality of the second branch sources are offset in the first direction, one end of the plurality of the second branch drains close to the receiving circuit is connected to the drain trunk, and one end of the plurality of the second branch drains far from the receiving circuit is disposed separated from the output wiring.
16. In Paragraph 13, The first source drain layer further includes a first low-potential line, a first clock line, and a second clock line connected to the output circuit, wherein the first low-potential line, the first clock line, and the second clock line are disposed at one end of the receiving circuit far from the output circuit, and the first low-potential line, the first clock line, and the second clock line are all extended along the first direction and arranged in the second direction. Here, the first low-potential line is positioned close to the receiving circuit, the second clock line is positioned far from the receiving circuit, and the first clock line is positioned between the first low-potential line and the second clock line in a display panel.
17. In Paragraph 13, The above display panel further includes a second source drain layer disposed on a side far from the first active layer of the first source drain layer, the second source drain layer includes a second low potential line and a first high potential line, and the second low potential line and the first high potential line are both extended along the first direction and arranged in the second direction. Here, the second low-potential line overlaps with a plurality of the first branch gates and a plurality of the second branch gates, and the second low-potential line is connected to a plurality of the first branch drains through a first connection hole, A display panel in which the first high potential line overlaps with the drain trunk and part of the receiving circuit, and the first high potential line is connected to the drain trunk through a second connection hole.
18. In Paragraph 17, A display panel in the second direction above where the width of the first low-potential line is smaller than the width of the second low-potential line.
19. In Paragraph 17, A display panel in the second direction above where the width of the first high potential line is greater than the width of the second low potential line.
20. In Paragraph 17, A display panel in which the size of the first connecting hole is smaller than the size of the second connecting hole.

Description

Display panel This application relates to the field of displays, and in particular to display panels. Existing OLED (Organic Light-Emitting Diode) displays are facing increasing demands regarding power consumption and screen-to-body ratio. Low Temperature Polysilicon Oxide (LTPO) technology is being used to reduce power consumption and increase the screen-to-body ratio. LTPO technology refers to a driving circuit that uses low-temperature polysilicon thin-film transistors and oxide thin-film transistors simultaneously, combining the advantages of both to reduce power consumption and leakage current. Currently, display devices using LTPO technology have a large number of film layers and require a large number of masks, making the process complex and increasing costs. An embodiment of the present application provides a display panel for solving the technical problems of the complex process of existing display devices using LTPO technology. To solve the above problem, the technical solution provided in this application is as follows. The present application proposes a display panel comprising a plurality of gate driving units, wherein the gate driving units include an output circuit, a receiving circuit, and a storage capacitor connected to each other, and the output circuit and the receiving circuit both include gate transistors, and the area of the gate transistor of the output circuit is larger than the area of the gate transistor of the receiving circuit. Here, at least one active portion of the gate transistor is located in the first active layer, one electrode plate of the storage capacitor is located in the second active layer, the gate of the gate transistor and the other electrode plate of the storage capacitor are located in the first gate layer, the first gate layer is disposed between the first active layer and the second active layer, and the materials of the first active layer and the second active layer are different from each other. FIG. 1 is a schematic diagram of the first structure of the display panel of the present application. FIG. 2 is an equivalent circuit diagram of the pixel driving circuit of the display panel of the present application. FIG. 3 is a schematic diagram of the second structure of the display panel of the present application. FIG. 4 is a schematic diagram of the third structure of the display panel of the present application. FIG. 5 is an equivalent circuit diagram of the gate driving circuit of the display panel of the present application. FIG. 6 is a schematic diagram of the film layer of the display panel of the present application. FIG. 7 is a film layer of the first gate layer of the display panel of the present application. FIG. 8 is a film layer of the first active layer of the display panel of the present application. FIG. 9 is a laminated view of the film layers of the first active layer and the first gate layer of the display panel of the present application. FIG. 10 is a film layer of the second active layer of the display panel of the present application. FIG. 11 is a laminated view of the film layers of the first active layer, the second active layer, and the first gate layer of the display panel of the present application. FIG. 12 is a film layer of the second gate layer of the display panel of the present application. FIG. 13 is a laminated view of the film layers of the first active layer, second active layer, first gate layer, and second gate layer of the display panel of the present application. FIG. 14 is a film layer of the first source drain layer of the display panel of the present application. FIG. 15 is a laminated view of the film layers of the first active layer, second active layer, first gate layer, second gate layer and first source drain layer of the display panel of the present application. FIG. 16 is a film layer of the second source drain layer of the display panel of the present application. FIG. 17 is a laminated view of the film layers of the first active layer, second active layer, first gate layer, second gate layer, first source drain layer and second source drain layer of the display panel of the present application. The technical methods of the embodiments of the present application are described clearly and completely below with reference to the accompanying drawings. By definition, the described embodiments are only a part of the embodiments of the present application and not all of them. All other embodiments obtained by a person skilled in the art without creative effort based on the embodiments of the present application fall within the scope of protection of the present application. Furthermore, it should be understood that the specific embodiments described herein are used merely to explain and interpret the present application, and are not intended to limit the present application. In the description of this application, the directional or positional relationships indicated by terms such as “length,” “width,” “thickness,”