KR-20260067356-A - Display panel and display device

Abstract

The present application discloses a display panel and a display device, wherein the gate driving unit of the display panel includes an output circuit, a receiving circuit, and a storage capacitor connected to each other, and both the output circuit and the receiving circuit include a gate transistor, the active part of the gate transistor is located in a first active layer, one electrode plate of the storage capacitor is located in a second active layer, the gate of the gate transistor and the other electrode plate of the storage capacitor are located in a first gate layer, and the first gate layer, the first active layer, and the second active layer are all disposed on different layers.

Inventors

• 장, 위헝
• 리우, 항

Assignees

• 우한 차이나 스타 옵토일렉트로닉스 세미컨덕터 디스플레이 테크놀로지 컴퍼니 리미티드

Dates

Publication Date

20260512

Application Date

20241108

Priority Date

20241104

Claims (20)

1. A display panel comprising a plurality of gate driving units, wherein the gate driving unit comprises an output circuit, a receiving circuit, and a storage capacitor connected to each other, the output circuit comprises a first output transistor and a second output transistor connected to each other, the drain of the first output transistor is connected to a clock line, the drain of the second output transistor is connected to a high potential line, and the area of the first output transistor is larger than the area of the second output transistor. Here, the output circuit and the receiving circuit both include a gate transistor, the active portion of the gate transistor is located in a first active layer, one electrode plate of the storage capacitor is located in a second active layer, the gate of the gate transistor and the other electrode plate of the storage capacitor are located in a first gate layer, and the first gate layer, the first active layer, and the second active layer are all disposed on different layers, forming a display panel.
2. In paragraph 1, The receiving circuit includes a first node control module, and the first output transistor and the first node control module are connected to a first node, and Here, the storage capacitor includes a first capacitor, the first capacitor includes a first electrode plate and a second electrode plate, the first electrode plate is connected to the source of the first output transistor, the second electrode plate is connected to the first node, the first electrode plate is located in the second active layer, and the second electrode plate is located in the first gate layer, forming a display panel.
3. In paragraph 2, The receiving circuit includes a second node control module, and the second output transistor and the second node control module are connected to the second node, and Here, the storage capacitor includes a second capacitor, the second capacitor includes a third electrode plate and a fourth electrode plate, the third electrode plate is connected to the high potential line and the fourth electrode plate is connected to the second node, the third electrode plate is located in the second active layer and the fourth electrode plate is located in the first gate layer, a display panel.
4. In Paragraph 3, A display panel in which the overlapping area of the first electrode plate and the second electrode plate is larger than the overlapping area of the third electrode plate and the fourth electrode plate.
5. In Paragraph 3, The first gate layer includes a first gate of the first output transistor and a second gate of the second output transistor, and the first gate and the second gate are arranged in a first direction, Here, a display panel in which the area of the first gate is larger than the area of the second gate.
6. In paragraph 5, The first gate comprises a first trunk gate and at least two first branch gates connected to the first trunk gate, wherein the first trunk gate extends along the first direction, the first branch gate extends along the second direction, and at least two first branch gates are spaced apart in the first direction. The second gate includes a second trunk gate and a second branch gate connected to the second trunk gate, the second trunk gate and the second branch gate extend along the second direction, the first branch gate and the second branch gate are spaced apart in the first direction, and the first trunk gate and the second trunk gate are spaced apart in the first direction. Here, a portion of the first trunk gate and the first branch gate is multiplexed to the second electrode plate, a portion of the second trunk gate and the second branch gate is multiplexed to the fourth electrode plate, the second direction is parallel to the scan line of the display panel, and the angle formed by the first direction and the second direction is greater than 0° and less than or equal to 90°.
7. In paragraph 6, The first active layer comprises a first active portion of the first output transistor and a second active portion of the second output transistor, wherein both the first active portion and the second active portion extend along the first direction, and the first active portion and the second active portion are connected to each other. Here, a display panel in which the first active part and a plurality of the first branch gates partially overlap, and the second active part and a plurality of the second branch gates partially overlap.
8. In Paragraph 7, A display panel in which the width of the first active part in the second direction is larger than the width of the second active part.
9. In paragraph 6, The second active layer comprises a first electrode plate of the first capacitor and a third electrode plate of the second capacitor, and Here, at least a portion of the outer contour of the first electrode plate extends outward relative to the outer contour of the second electrode plate, and at least a portion of the outer contour of the third electrode plate extends outward relative to the outer contour of the fourth electrode plate, forming a display panel.
10. In Paragraph 9, The second electrode plate comprises a first trunk electrode plate and at least two first branch electrode plates connected to the first trunk electrode plate, wherein the first trunk electrode plate extends along the first direction and at least two first branch electrode plates extend along the second direction, and a plurality of the first branch electrode plates are spaced apart in the first direction. Here, the first trunk electrode plate overlaps at least partially with the first trunk gate, the first branch electrode plate overlaps at least partially with the corresponding first branch gate, and the length of the first branch electrode plate is shorter than the length of the first branch gate, forming a display panel.
11. In paragraph 6, The display panel further includes a first source-drain layer disposed on a side of the second active layer far from the first active layer, and the first source-drain layer includes a first source and a first drain of the first output transistor and a second source and a second drain of the second output transistor. The first drain includes a first branch drain, and the first source includes a first branch source, and The second drain includes a second branch drain, and the second source includes a second branch source; the first branch drain, the first branch source, the second branch drain, and the second branch drain all extend along the second direction and are spaced apart in the first direction. Here, the first branch gate has the first branch drain and the first branch source disposed on both sides of the second direction, the second branch gate has the second branch drain and the second branch source disposed on both sides of the second direction, and the second branch source close to the first output transistor is multiplexed into the first branch source, forming a display panel.
12. In Paragraph 11, The first source drain layer further comprises a source trunk extending along the first direction, the first branch source is connected to the source trunk, and at least a portion of the source trunk overlaps with the first capacitor in a display panel.
13. In Paragraph 11, The above display panel further includes a second source drain layer disposed on a side far from the first active layer of the first source drain layer, the second source drain layer includes a low potential line and a high potential line, the low potential line and the high potential line extend along the first direction and are arranged in the second direction, Here, the high potential line has a portion that overlaps with the output circuit, and the low potential line has a portion that overlaps with the receiving circuit, forming a display panel.
14. In Paragraph 13, A display panel in which the width of the high potential line in the second direction is greater than the width of the low potential line.
15. In Paragraph 13, The second source drain layer further includes a plurality of clock lines disposed between the low potential line and the high potential line, and the plurality of clock lines extend along the first direction and are arranged in the second direction, Here, a display panel having some of the plurality of clock lines overlapping with the output circuit and some of the plurality of clock lines overlapping with the receiving circuit.
16. In paragraph 15, A plurality of the above clock lines include a first clock line, a second clock line, a third clock line, and a fourth clock line arranged at intervals, wherein the first clock line has a portion overlapping with the output circuit, and the second clock line, the third clock line, and the fourth clock line have portions overlapping with the receiving circuit. Here, each of the gate driving units is a display panel connected to two different clock lines among the first clock line, the second clock line, the third clock line, and the fourth clock line.
17. In paragraph 15, A display panel in which, in the second direction above, the width of the clock line is greater than the width of the low potential line, and the width of the clock line is smaller than the width of the high potential line.
18. In any one of paragraphs 1 through 17, The above receiving circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and an eighth transistor, and The gate of the first transistor is connected to a first type clock line, the drain of the first transistor is connected to a low potential line, and the source of the first transistor is connected to a second node, and The gate of the second transistor is connected to a first type clock line, the drain of the second transistor is connected to an initial signal line or the output terminal of the gate driving unit of a previous level, and the source of the second transistor is connected to a third node, and The gate of the third transistor is connected to the third node, the drain of the third transistor is connected to the first type clock line, and the source of the third transistor is connected to the second node, and The gate of the fourth transistor is connected to the second type clock line, the drain of the fourth transistor is connected to the source of the fifth transistor, and the source of the fourth transistor is connected to the third node, and The gate of the fifth transistor is connected to the second node, and the drain of the fifth transistor is connected to a high-potential line, and The gate of the eighth transistor is connected to a low-potential line, the drain of the eighth transistor is connected to a third node, and the source of the eighth transistor is connected to a first node, and Here, the drain of the first output transistor is a display panel connected to the second type clock line.
19. In Paragraph 18, The first gate layer of the display panel includes the gate of the second transistor, the first active layer of the display panel includes the active portion of the second transistor, and the gate of the second transistor extends along a second direction, Here, the active portion of the second transistor comprises at least two active branches connected to each other, the at least two active branches are arranged side by side along the second direction, and the gate of the second transistor has a portion that overlaps with both of the at least two active branches, forming a display panel.
20. A display device comprising a display panel according to any one of claims 1 to 19.

Description

Display panel and display device This application relates to the field of displays, and in particular to display panels and display devices. Existing OLED (Organic Light-Emitting Diode) displays are facing increasing demands regarding power consumption and screen-to-body ratio. Low Temperature Polysilicon Oxide (LTPO) technology is being used to reduce power consumption and increase the screen-to-body ratio. LTPO technology refers to a driving circuit that uses low-temperature polysilicon thin-film transistors and oxide thin-film transistors simultaneously, combining the advantages of both to reduce power consumption and leakage current. Currently, display devices using LTPO technology have a large number of film layers and require a large number of masks, making the process complex and increasing costs. FIG. 1 is a schematic diagram of the first structure of the display panel of the present application. FIG. 2 is an equivalent circuit diagram of the pixel driving circuit of the display panel of the present application. FIG. 3 is a schematic diagram of the second structure of the display panel of the present application. FIG. 4 is a schematic diagram of the third structure of the display panel of the present application. FIG. 5 is an equivalent circuit diagram of the gate driving circuit of the display panel of the present application. FIG. 6 is a schematic diagram of the film layer of the display panel of the present application. FIG. 7 is a film layer of the first gate layer of the display panel of the present application. FIG. 8 is a film layer of the first active layer of the display panel of the present application. FIG. 9 is a laminated view of the film layers of the first active layer and the first gate layer of the display panel of the present application. FIG. 10 is a film layer of the second active layer of the display panel of the present application. FIG. 11 is a laminated view of the film layers of the first active layer, the second active layer, and the first gate layer of the display panel of the present application. FIG. 12 is a film layer of the second gate layer of the display panel of the present application. FIG. 13 is a laminated view of the film layers of the first active layer, the second active layer, the first gate layer, and the second gate layer of the display panel of the present application. FIG. 14 is a film layer of the first source drain layer of the display panel of the present application. FIG. 15 is a laminated view of the film layers of the first active layer, the second active layer, the first gate layer, the second gate layer, and the first source drain layer of the display panel of the present application. FIG. 16 is a film layer of the second source drain layer of the display panel of the present application. FIG. 17 is a laminated view of the film layers of the first active layer, the second active layer, the first gate layer, the second gate layer, the first source drain layer, and the second source drain layer of the display panel of the present application. FIG. 18 is a diagram showing the connection between the gate driving unit and the clock line of a continuous 4-level display panel of the present application. The technical methods of the embodiments of the present application are described clearly and completely below with reference to the accompanying drawings. By definition, the described embodiments are only a part of the embodiments of the present application and not all of them. All other embodiments obtained by a person skilled in the art without creative effort based on the embodiments of the present application fall within the scope of protection of the present application. Furthermore, it should be understood that the specific embodiments described herein are used merely to explain and interpret the present application, and are not intended to limit the present application. In the description of this application, the directional or positional relationships indicated by terms such as “length,” “width,” “thickness,” “top,” “bottom,” “front,” “back,” “left,” “right,” “top,” “bottom,” “inside,” and “outside” are based on the directional or positional relationships depicted in the drawings and are intended only to facilitate and simplify the description of this application. It should be understood that this does not indicate or imply that the mentioned device or element must have a specific direction or be configured and operated in a specific direction, and therefore should not be interpreted as a limitation of this application. Furthermore, the terms “First” and “Second” are used for descriptive purposes only and should not be understood as indicating or implying relative importance, or implying the quantity of the indicated technical features. Accordingly, the features defined as “First” and “Second” may explicitly or implicitly include one or more features. In the description of this application, “plural” means two or more, and at least one means one,