KR-20260067357-A - Memory System Operation Method and Device

Abstract

A method, device, device, and system for operating a memory system are provided. In one embodiment, the memory system includes a memory device comprising a plurality of memory blocks and a memory controller coupled to the memory device. The memory controller is configured to identify a first memory block among the plurality of memory blocks, wherein the first memory block contains specific data that is invalid. The memory controller may be configured to increase the priority level of the first memory block among the plurality of memory blocks and to perform garbage collection on the memory device based on the priority levels of the plurality of memory blocks.

Inventors

• 허 하오
• 탄 화

Assignees

• 양쯔 메모리 테크놀로지스 씨오., 엘티디.

Dates

Publication Date

20260512

Application Date

20241104

Claims (20)

1. As a memory system, A memory device comprising a plurality of memory blocks; and Memory controller coupled to the above memory device Includes, and the memory controller is: Identifying a first memory block among the plurality of memory blocks above - where the first memory block contains specific invalid data - ; Increasing the priority level of the first memory block among the plurality of memory blocks; and A memory system configured to perform garbage collection on the memory device based on the priority levels of the plurality of memory blocks.
2. In paragraph 1, A memory system in which the above specific data includes replay protection memory block (RPMB) data.
3. In paragraph 1 or 2, A memory system in which the above specific data becomes invalid when new data is written to the same logical address as the above specific data.
4. In any one of paragraphs 1 through 3, The above memory controller It is configured to identify the first memory block by checking a mark bit corresponding to the first memory block, and A memory system in which the above-mentioned indicator bit indicates whether the first memory block contains the specific data that is invalid.
5. In any one of paragraphs 1 through 4, The above memory controller is: By decreasing the first effective page count (VPC) of the first memory block, the priority level of the first memory block is increased; and A memory system configured to perform a first garbage collection operation on a first memory block before a second memory block having a second VPC larger than the first VPC.
6. In any one of paragraphs 1 through 5, The above memory controller is: Receiving a fuzzy command to erase specific invalid data from the above memory device; and A memory system configured to transmit a response indicating that the specific invalid data in the memory device has been erased.
7. In paragraph 6, The above memory controller is: A memory system configured to erase specific invalid data from a corresponding memory block during garbage collection before receiving the above fuzzy command.
8. In any one of paragraphs 1 through 7, The above memory controller is: A memory system configured to perform garbage collection on the memory device when the memory device is idle.
9. In any one of paragraphs 1 through 8, The above memory controller is: A memory system configured to perform a first garbage collection operation on a first memory block by transmitting one or more commands to move valid data from the first memory block to a target memory block of the memory device and to erase the first memory block.
10. As a memory controller, processor; and A first interface configured to be coupled to a memory device Includes, Here, the processor is configured to perform garbage collection on the memory device based on the priority levels of a plurality of memory blocks of the memory device, and Here, the first interface is: Transmit one or more read commands to read valid data from a first memory block among the plurality of memory blocks, wherein the first memory block contains specific invalid data, and among the plurality of memory blocks, the first memory block has an increased priority level based on the fact that the first memory block contains the specific invalid data. A memory controller configured to transmit one or more write commands to write the valid data read from the first memory block to a target memory block of the memory device.
11. In Paragraph 10, The above processor is: Identifying the first memory block from the plurality of memory blocks; A memory controller configured to increase the priority level of the first memory block among the plurality of memory blocks.
12. In Paragraph 11, The above processor is: By decreasing the first effective page count (VPC) of the first memory block, the priority level of the first memory block is increased; A memory controller configured to perform a first garbage collection operation on the first memory block before a second memory block having a second VPC larger than the first VPC.
13. In any one of paragraphs 10 through 12, The memory controller above includes a second interface coupled to a host, and the second interface is: Receiving a fuzzy command to erase specific invalid data from the above memory device; A memory controller configured to transmit a response indicating that the specific invalid data in the memory device has been erased.
14. In Paragraph 13, A memory controller configured such that the processor erases the specific invalid data from the corresponding memory block during garbage collection before receiving the fuzzy command.
15. In any one of paragraphs 10 through 14, A memory controller configured such that the processor performs garbage collection on the memory device when the memory device is idle.
16. In any one of paragraphs 10 through 15, The above specific data is a memory controller containing replay protection memory block (RPMB) data.
17. In any one of paragraphs 10 through 16, A memory controller in which the above specific data becomes invalid when new data is written to the same logical address as the above specific data.
18. In any one of paragraphs 10 through 17, The above processor is: A memory controller configured to identify the first memory block by checking a mark bit corresponding to the first memory block, wherein the mark bit indicates whether the first memory block contains the specific data that is invalid.
19. In any one of paragraphs 10 through 18, The above processor is: A memory controller configured to perform a first garbage collection operation on a first memory block by transmitting one or more commands to move valid data from the first memory block to a target memory block of the memory device and to erase the first memory block.
20. As a method of operation of a memory system, A step of identifying a first memory block among a plurality of memory blocks of a memory device of the above-described memory system - wherein the first memory block includes specific invalid data - ; A step of increasing the priority level of the first memory block among the plurality of memory blocks; and A step of performing garbage collection on the memory device based on the priority levels of the plurality of memory blocks. A method of operation of a memory system including

Description

Memory System Operation Method and Device The present disclosure generally relates to memory devices and memory systems, and in particular to the operation of memory systems. Flash memory is a low-cost, high-density, non-volatile solid-state storage medium that can be electrically erased and reprogrammed. Flash memory includes NOR flash memory and NAND flash memory. Various operations can be performed by flash memory, such as program (write) or read operations. The operations performed by flash memory can affect the temperature of the flash memory. The present disclosure includes the operation of a memory system, for example, a method, apparatus, and system for managing fuzzy instructions in a memory system. One aspect of the present disclosure provides a memory device comprising a plurality of memory blocks and a memory controller coupled to the memory device. The memory controller is configured to identify a first memory block among the plurality of memory blocks, wherein the first memory block contains specific invalid data. The memory controller is further configured to increase the priority level of the first memory block among the plurality of memory blocks and to perform garbage collection on the memory device based on the priority levels of the plurality of memory blocks. In some embodiments, the specific data includes replay protection memory block (RPMB) data. In some implementations, the specific data becomes invalid when new data is written to the same logical address as the specific data. In some embodiments, the memory controller is configured to identify the first memory block by checking a mark bit corresponding to the first memory block. The mark bit indicates whether the first memory block contains the specific data that is invalid. In some embodiments, the memory controller is configured to increase the priority level of the first memory block by decreasing the first effective page count (VPC) of the first memory block and to perform a first garbage collection operation on the first memory block before a second memory block having a second VPC greater than the first VPC. In some embodiments, the memory controller is configured to receive a fuzzy command to erase specific invalid data in the memory device and to transmit a response indicating that the specific invalid data in the memory device has been erased. In some embodiments, the memory controller is configured to erase the specific invalid data from the corresponding memory block during garbage collection before receiving the fuzzy command. In some embodiments, the memory controller is configured to perform garbage collection on the memory device when the memory device is idle. In some embodiments, the memory controller is configured to perform a first garbage collection operation on the first memory block by transmitting one or more commands to move valid data from the first memory block to a target memory block of the memory device and to erase the first memory block. Another aspect of the present disclosure features a memory controller. The memory controller includes a processor and a first interface coupled to a memory device. The processor is configured to perform garbage collection on the memory device based on priority levels of a plurality of memory blocks of the memory device. The first interface is configured to transmit one or more read commands for reading valid data from a first memory block among the plurality of memory blocks. The first memory block contains specific invalid data. Among the plurality of memory blocks, the first memory block has an increased priority level based on the fact that the first memory block contains the specific invalid data. The first interface is further configured to transmit one or more write commands for writing the valid data read from the first memory block to a target memory block of the memory device. In some embodiments, the processor is configured to identify the first memory block from the plurality of memory blocks and increase the priority level of the first memory block among the plurality of memory blocks. In some embodiments, the processor is configured to increase the priority level of the first memory block by decreasing the first effective page count (VPC) of the first memory block and to perform a first garbage collection operation on the first memory block before a second memory block having a second VPC greater than the first VPC. In some embodiments, the memory controller includes a second interface coupled to a host. The second interface is configured to receive a fuzzy command for erasing specific invalid data from the memory device and to transmit a response indicating that the specific invalid data has been erased from the memory device. In some embodiments, the processor is configured to erase the specific invalid data from the corresponding memory block during garbage collection before receiving the fuzzy command. In some embodiments, the processor is configured