KR-20260067358-A - Method and device for operating a memory system

Abstract

A method, device, and system for managing a memory device are provided. In one aspect, the memory system may include a memory device comprising a memory page and a memory controller coupled to the memory device. The memory controller is configured to transmit a first command to the memory device instructing it to identify dummy data, and in response to receiving a response from the memory device instructing that the first memory page is a zero page, determine the data contained in the first memory page as dummy data.

Inventors

• 탕 싱웨이
• 궈 루
• 런 쿤
• 뤄 원

Assignees

• 양쯔 메모리 테크놀로지스 씨오., 엘티디.

Dates

Publication Date

20260512

Application Date

20241104

Claims (20)

1. As a memory system, A memory device including memory pages; and Memory controller coupled to the above memory device Includes, The above memory controller is, A first command instructing the memory device to identify dummy data is transmitted, and A memory system configured to determine data contained in the first memory page as dummy data in response to receiving a response from the memory device indicating that the first memory page is a zero page.
2. In paragraph 1, The above memory controller additionally, It is configured to transmit a second command instructing to write dummy data to a second memory page, and The above memory device is, A memory system configured to program the second memory page as a zero page in response to receiving the second command, wherein the threshold voltage of the memory cell of the zero page is higher than a preset level, and the preset level is higher than a start read level for reading the second memory page.
3. In paragraph 2, A memory system in which the second command instructs to program the second memory page based on a single-level cell (SLC) mode.
4. In paragraph 3, Programming the second memory page based on the above SLC mode is, A memory system comprising programming a memory cell of the second memory page above the preset level using a single program pulse.
5. In any one of paragraphs 2 through 4, A memory system in which the low density parity check (LDPC) encoder of the memory controller is disabled when programming the second memory page.
6. In any one of paragraphs 1 through 5, The above memory device is, A memory system configured to transmit a response indicating that the first memory page is a zero page, without transmitting data contained in the first memory page to the memory controller.
7. In any one of paragraphs 1 through 6, The above memory device is, Based on the start read voltage, a read operation is performed on the first memory page, and Determining the quantity of failed memory cells in the first memory page above - the threshold voltage of the failed memory cells is lower than the start read voltage -, A memory system configured to transmit a response indicating that the first memory page is a zero page in response to determining that the number of the failed memory cells is less than a threshold.
8. In any one of paragraphs 1 through 7, A memory system configured such that the memory controller transmits the first command during the garbage collection operation of the memory system.
9. In any one of paragraphs 2 through 5, A memory system in which the memory controller is configured to transmit the second command during power loss protection operation, and the second memory page is included in an open memory block.
10. In any one of paragraphs 2 through 5, The memory controller is configured to transmit the second command after a program operation for programming user data into one or more memory pages, and the second memory page is immediately following the last memory page of the one or more memory pages, in a memory system.
11. As a memory controller, At least one processor and interface Includes, The above-mentioned at least one processor is, A first command instructing to identify dummy data is transmitted to a memory device through the interface, and A memory controller configured to determine data contained in the first memory page as dummy data in response to receiving a response from the memory device through the above interface indicating that the first memory page is a zero page.
12. In Paragraph 11, The above memory controller is, A memory controller configured to transmit a second command instructing to write dummy data to a second memory page, wherein the second command instructs to program the second memory page based on a single-level cell (SLC) mode.
13. In Paragraph 12, A memory controller in which the low density parity check (LDPC) encoder of the memory controller is disabled when programming the second memory page.
14. In Article 12 or Article 13, The memory controller is configured to transmit the second command during power loss protection operation, and the second memory page is included in an open memory block.
15. In any one of paragraphs 12 through 14, The memory controller is configured to transmit the second command after a program operation for programming user data into one or more memory pages, wherein the second memory page is immediately following the last memory page of the one or more memory pages.
16. In any one of paragraphs 11 through 15, The memory controller is configured to transmit the first command during a garbage collection operation.
17. As a method of operating a memory system, A step of transmitting a first command instructing to identify dummy data from a memory controller of the memory system to a memory device of the memory system; and A step in which the memory controller determines the data contained in the first memory page as dummy data in response to receiving a response from the memory device indicating that the first memory page of the memory device is a zero page. A method for operating a memory system including
18. In Paragraph 17, A step of performing a read operation on the first memory page based on the start read voltage; A step of determining the quantity of failed memory cells in the first memory page above - the threshold voltage of the failed memory cells is lower than the start read voltage -; and In response to determining that the number of the aforementioned failed memory cells is less than a threshold value, the step of transmitting a response from the memory device to the memory controller indicating that the first memory page is a zero page. A method for operating a memory system that includes more.
19. In paragraph 17 or 18, A step of transmitting a second command from the memory controller to the memory device instructing to write dummy data to a second memory page of the memory device; and The above memory device programs the second memory page as a zero page. Includes, A method of operating a memory system in which the threshold voltage of the memory cell of the above zero page is higher than a preset level, and the preset level is higher than a start read level for reading the above second memory page.
20. In any one of paragraphs 17 through 19, A step of not transmitting data contained in the first memory page, and transmitting a response from the memory device to the memory controller indicating that the first memory page is a zero page. A method for operating a memory system including

Description

Method and device for operating a memory system The present disclosure generally relates to memory devices and memory systems, and more specifically to programming and identifying dummy data in a memory system. Flash memory is a low-cost, high-density, non-volatile solid-state storage medium that can be electrically erased and reprogrammed. Flash memory includes NOR flash memory and NAND flash memory. Various operations, such as programming (writing) and erasing, can be performed by flash memory to change the threshold voltage of each memory cell to individual levels. In the case of NAND flash memory, erasing operations can be performed at the memory block level, programming operations can be performed at the page level, and reading operations can be performed at the page level. The present disclosure includes a method, apparatus, and system for programming and identifying dummy data in a memory system. One aspect of the present disclosure features a memory system comprising a memory device including a memory page and a memory controller coupled to the memory device. The memory controller is configured to transmit a first command to the memory device instructing it to identify dummy data, and to determine the data contained in the first memory page as dummy data in response to receiving a response from the memory device indicating that the first memory page is a zero page. In some embodiments, the memory controller is additionally configured to transmit a second command instructing to write dummy data to the second memory page. The memory device is configured to program the second memory page as the zero page in response to receiving the second command. The threshold voltage of the memory cell of the zero page is higher than a preset level. The preset level is higher than the starting read level for reading the second memory page. In some embodiments, the second command instructs to program the second memory page based on a single-level cell (SLC) mode. In some embodiments, programming a second memory page based on an SLC mode includes programming a memory cell of the second memory page above a preset level using a single program pulse. In some embodiments, when programming the second memory page, the low density parity check (LDPC) encoder of the memory controller is disabled. In some embodiments, the memory device is configured not to transmit data contained in the first memory page to the memory controller, but to transmit a response indicating that the first memory page is a zero page. In some embodiments, the memory device is configured to perform a read operation on a first memory page based on a start read voltage, determine the number of failed memory cells in the first memory page—where the threshold voltage of the failed memory cells is lower than the start read voltage—and, in response to determining that the number of failed memory cells is less than the threshold, transmit a response indicating that the first memory page is a zero page. In some embodiments, the memory controller is configured to transmit a first command during the garbage collection operation of the memory system. In some embodiments, the memory controller is configured to transmit a second command during power loss protection operation. The second memory page is included in an open memory block. In some embodiments, the memory controller is configured to send a second command after a program operation to program user data into one or more memory pages. The second memory page follows immediately after the last of the one or more memory pages. Another aspect of the present disclosure features a memory controller. The memory controller includes an interface with at least one processor. The at least one processor is configured to transmit a first command to a memory device through the interface to identify dummy data, and to determine the data contained in the first memory page as dummy data in response to receiving a response from the memory device through the interface indicating that the first memory page is a zero page. In some embodiments, the memory controller is configured to transmit a second command instructing to write dummy data to a second memory page. The second command instructs to program the second memory page based on a single-level cell (SLC) mode. In some implementations, the low density parity check (LDPC) encoder of the memory controller is disabled when programming the second memory page. In some embodiments, the memory controller is configured to transmit a second command during power loss protection operation. The second memory page is included in an open memory block. In some embodiments, the memory controller is configured to send a second command after a program operation to program user data into one or more memory pages. The second memory page follows immediately after the last of the one or more memory pages. In some implementations, the memory controller is configured to send a first command during a