KR-20260067363-A - Method and system for resolution expansion of an FPGA-based time-to-digital converter using time-bin start-time calculation and iterative interleaving

KR20260067363AKR 20260067363 AKR20260067363 AKR 20260067363AKR-20260067363-A

Abstract

The present invention relates to a method for expanding and correcting the resolution of an FPGA-based time-to-digital converter. By performing a code density test for each of a plurality of tap delay line units to determine the width and start time of the time bins, and by globally aligning and interleaving them, a high resolution exceeding the physical limitations of individual units is achieved.

Inventors

박병권
박선우
김은성
윤지원

Assignees

에스디티 주식회사

Dates

Publication Date: 20260512
Application Date: 20260424

Claims (16)

As a method for extending the resolution of an FPGA-based time-to-digital converter (TDC), A correction controller determines the width of each time bin (25) included in each tap delay line unit from time bin frequency data obtained through a code density test for each of the plurality of tap delay line units; The correction controller calculates the start time of each time bin included in each tap delay line unit based on the width of each time bin determined above; and The correction controller performs the step of globally sorting the plurality of time bins belonging to the plurality of tap delay line units according to the order of magnitude of the calculated start times and interleaving them into a single integrated delay sequence; Includes, The time-to-digital converter is characterized by being configured to measure the width of the pulse to be measured at a higher resolution than the resolution of each tap delay line unit alone by converting the width of the pulse to be measured into a digital code or time value using the interleaved integrated delay sequence. Method for expanding the resolution of a time-to-digital converter.
In paragraph 1, The step of determining the width of each time bin above is, The input signal generating part (10) of the time-to-digital converter applies a random input signal that is asynchronous with the sampling clock (11) to each of the tap delay line units; The correction controller above collects and accumulates a sample count value, which is the number of times a signal transition is detected in each time bin for the random input signal; and The correction controller calculates the ratio of the sample count value of a specific time bin to the total sum of the collected sample count values, and determines the actual physical time width of the corresponding time bin as the width (W); Characterized by including, Method for expanding the resolution of a time-to-digital converter.
In paragraph 2, The step of calculating the start time of each of the above time bins is, The correction controller sequentially accumulates and sums the widths of the plurality of time bins arranged along the actual propagation path of the signal within each of the tap delay line units; and The correction controller determines the start time of a specific time bin as the sum of the widths (W), which are temporal offsets taken from the input point of the tap delay line unit to the time bin immediately preceding the specific time bin; Characterized by including, Method for expanding the resolution of a time-to-digital converter.
In paragraph 1, Prior to the above-mentioned global alignment step, The correction controller further comprises a partial order reconstruction step that analyzes the code density test data to restore the actual order of time bins scrambled by physical wiring path delays within each tap delay line unit. Method for expanding the resolution of a time-to-digital converter.
In paragraph 1, The correction controller calculates the physical delay deviation (i.e., differential nonlinearity error) of each time bin by calculating, for each time bin on the integrated delay sequence, the deviation of the width (W) of the time bin relative to the average width of all time bins in the integrated delay sequence determined based on the frequency in the code density test; The correction controller corrects the nonlinearity of the integrated delay sequence caused by the physical arrangement and wiring characteristics of the FPGA hardware resources by multiplying a weighting factor inversely proportional to the physical delay deviation by the frequency in the code density test; Characterized by further including, Method for expanding the resolution of a time-to-digital converter.
In paragraph 1, The correction controller comprises a filtering step of identifying ultra-narrow bins in which the calculated width (W) is less than a preset threshold, and excluding the identified ultra-narrow bins from the integrated delay sequence; Characterized by further including, Method for expanding the resolution of a time-to-digital converter.
In paragraph 1, The above plurality of tap delay line units are characterized by being in a state where the time bin sequence within each individual unit is corrected to match the physical actual arrangement through a Directed Acyclic Graph (DAG)-based Partial Order Reconstruction (POR) algorithm. Method for expanding the resolution of a time-to-digital converter.
As an FPGA-based time-to-digital conversion system, A plurality of tap delay line (20) units provided in an FPGA, which propagate a signal to be measured to generate sampling data; A correction controller (170) that processes data obtained from the plurality of tap delay line units; and A hardware encoder (140) that converts the width of an input pulse into a digital code or time value using the above integrated delay sequence information; Includes, The above correction controller is, The width of each time bin (25) is determined from the frequency data per time bin obtained through a code density test for each of the above plurality of tap delay line units, and Based on the width determined above, the relative start time of each time bin is calculated, and The time bins belonging to the plurality of tap delay line units are configured to generate a single integrated delay sequence by globally aligning them according to the order of magnitude of the calculated start times, and The above hardware encoder is characterized by measuring the width of the pulse at a resolution higher than the resolution of each tap delay line unit alone, based on the integrated delay sequence. Time-to-digital converter system.
In paragraph 8, An input signal generating part (10) that applies a random input signal asynchronous with the sampling clock (11) to each of the above tap delay line units; Includes more, The above correction controller is, For the above random input signal, sample count values, which are the number of times a signal transition is detected in each time bin, are accumulated and collected, and Characterized by being configured to determine the actual physical time width of a specific time bin as the width (W) by calculating the ratio occupied by the sample count value of a specific time bin relative to the total sum of the collected sample count values. Time-to-digital converter system.
In Paragraph 9, The above correction controller is, The widths of the plurality of time bins arranged along the actual propagation path of the signal within each of the above-mentioned tap delay line units are sequentially accumulated and summed, Characterized by being configured to determine the sum of the widths, which is the temporal offset taken from the input point of the above-mentioned tap delay line unit to the time bin immediately preceding the specific time bin, as the start time (t) of the specific time bin. Time-to-digital converter system.
In paragraph 8, The correction controller is characterized by including a Partial Order Reconstruction module that, prior to global alignment, analyzes the code density test data to restore the actual order of time bins scrambled by physical wiring path delays within each tap delay line unit. Time-to-digital converter system.
In paragraph 8, The above correction controller is, For each time bin on the integrated delay sequence, the deviation of the width (W) of the time bin relative to the average width of all time bins in the integrated delay sequence, determined based on the frequency in the code density test, is calculated to calculate the physical delay deviation (i.e., differential nonlinearity error) of each time bin, and Characterized by being configured to correct the nonlinearity of the integrated delay sequence caused by the physical placement and wiring characteristics of the FPGA hardware resources by multiplying the frequency in the code density test by a weighting factor inversely proportional to the physical delay deviation. Time-to-digital converter system.
In paragraph 8, The correction controller is characterized by being configured to perform a filtering function that identifies ultrafine bins in which the calculated width (W) is less than a preset threshold value and excludes the identified ultrafine bins from the integrated delay sequence. Time-to-digital converter system.
In paragraph 8, The plurality of tap delay line units are characterized by being provided in a state where the time bin sequence within each individual unit is corrected to match the physical actual arrangement by the correction controller that performs phase alignment based on a directed acyclic graph (DAG). Time-to-digital converter system.
A non-transient recording medium readable by a computing device, storing instructions that, when executed by a computing device, cause the computing device to perform a method of extending the resolution of a time-to-digital converter (TDC), A method for extending the resolution of the above time-to-digital converter (TDC) is, A step of determining the width of each time bin (25) included in each of the multiple tap delay line units from the frequency data per time bin obtained through a code density test for each of the multiple tap delay line units; A step of calculating the start time of each time bin included in each tap delay line unit based on the width of each time bin determined above; and A step of globally sorting the plurality of time bins belonging to the plurality of tap delay line units according to the order of the magnitude of the calculated start times and interleaving them into a single integrated delay sequence; Includes, The time-to-digital converter is characterized by being configured to measure the width of the pulse to be measured at a higher resolution than the resolution of each tap delay line unit alone by converting the width of the pulse to be measured into a digital code or time value using the interleaved integrated delay sequence. A non-transient recording medium readable by a computing device.
A non-transient recording medium readable by a computing device according to claim 15, characterized in that the computing device is a processing unit implemented inside the FPGA or an external computer device connected to communicate with the FPGA.

Description

Method and system for resolution expansion of an FPGA-based time-to-digital converter using time-bin start-time calculation and iterative interleaving The present invention relates to time-to-digital converter (TDC) technology in fields requiring high-resolution time interval measurement, such as LiDAR, medical imaging, and quantum information processing. In particular, it relates to a resolution improvement technology that overcomes physical resolution (LSB) limitations and achieves picosecond level or lower precision by utilizing the tap delay line (TDL) resources of an FPGA and interleaving multiple delay lines based on statistical start times. A single-tap delay-line-based time-to-digital converter samples the spatial location of a signal propagating through a chain of logic elements to divide a nanosecond clock period into fine time bins. However, the minimum resolution (LSB) of this method is determined by physical constraints such as the clock frequency and the propagation speed inherent to the internal components of the FPGA. Particularly when implementing ultra-high resolution at the picosecond (ps) level or below, minute variations in signal propagation and clock skew exert a dominant influence, which can fundamentally limit the measurement accuracy and effective resolution of the system. Korean registered patent KR 10-2767209, a prior art technology, aims to improve time resolution by aligning the element order of a thermometer code based on the data path delay measured from the output node of an input pulse to the output node of each flip-flop. While this method attempts to ensure monotonically increasing delay time, it relies primarily on static delay information such as timing reports, making it difficult to fully reflect the uncertainty of dynamic propagation delays occurring in actual operating environments. Furthermore, it fails to completely resolve the problem of missing codes where specific time bins are skipped during the signal detection process, which may limit the optimization of available bin resources. Hardware factors such as manufacturing process differences, voltage fluctuations, and temperature variations (PVT) cause variations in the physical propagation characteristics of internal FPGA carry logic resources, leading to nonlinear behavior. This results in technical nonlinearity, which is observed through frequency deviations in code density tests. These physical variations cause the mixing of signal arrival order along the delay path, resulting in ambiguous transitions in the thermometer code and causing a "missing code" phenomenon where specific time bins are not detected. This phenomenon exacerbates gaps in bin placement and temporal distortion during the process of merging multiple delay lines to expand resolution. Consequently, this can worsen the nonlinearity (DNL/INL) indicators of TDC and degrade the final time measurement precision. FIG. 1 is a configuration diagram illustrating the overall hardware configuration of a time-to-digital converter system based on repetitive time bin interleaving according to one embodiment of the present invention. FIG. 2 is a structural diagram illustrating in detail a tapping and sampling mechanism inside a delay line according to one embodiment of the present invention. FIG. 3 is a histogram illustrating the width distribution of each time bin obtained through a code density test according to one embodiment of the present invention. FIG. 4 is a conceptual diagram illustrating the principle of calculating the start time of each time bin according to one embodiment of the present invention. FIG. 5 is a conceptual diagram illustrating the process of interleaving time bins derived from a plurality of tap delay line units according to an embodiment of the present invention by globally aligning them based on a start time. FIG. 6 is a histogram showing the bin width distribution generated by applying the global alignment and interleaving steps according to one embodiment of the present invention to each of the first to fourth tap delay lines. FIG. 7 is a structural diagram illustrating an architecture that expands the time resolution of TDC in multiple units through hierarchical or iterative interleaving according to an embodiment of the present invention. FIG. 8 is a diagram illustrating a comparison of the application of ultrafine bin filtering technology according to one embodiment of the present invention before and after. FIG. 9 is a graph illustrating a second-order nonlinearity scaling correction model using weighting coefficients according to one embodiment of the present invention. FIG. 10 is a graph illustrating the improvement effects of differential nonlinearity and integral nonlinearity at each step of applying the correction technology according to one embodiment of the present invention. FIG. 11 is a graph showing the precision variation (or error distribution) of the results of measuring various time intervals with a physical c