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KR-20260067364-A - Analog feedback control-based semiconductor quantum computing device

KR20260067364AKR 20260067364 AKR20260067364 AKR 20260067364AKR-20260067364-A

Abstract

The present invention relates to a semiconductor spin qubit-based quantum computing device comprising a semiconductor quantum dot array (100) having a multilayer gate bank structure, a HEMT-based low-temperature amplifier (200), an analog CIM-based NPU (300), and a control unit (400). The low-temperature amplifier (200) directly applies an analog measurement signal of a qubit to a memory cell array (310) of the NPU (300) without an ADC through a level shifter (220), and the NPU (300) calculates a correction value by performing an analog MAC operation based on Ohm's law current summation, and forms a fully analog feedback loop that corrects the gate voltage in real time through a DAC (410) and a gate driver (420) of the control unit (400). Through this, the feedback delay is reduced to the level of tens of nanoseconds to complete the error correction loop within the qubit coherence time, and wiring delay is minimized through a direct connection structure based on 3D stacked packaging and TSV (500).

Inventors

  • 안범주

Assignees

  • 안범주

Dates

Publication Date
20260512
Application Date
20260425

Claims (9)

  1. In an ultra-low latency quantum computing device combining a semiconductor spin qubit array and an artificial intelligence accelerator, A semiconductor quantum dot array having a multilayer gate bank structure comprising a channel region in which a plurality of quantum dots are formed to confine a single electron, a first electrode layer including a barrier gate for controlling a potential barrier, and a second electrode layer including a plunger gate for controlling the quantum dot potential; A low-temperature amplifier based on a high electron mobility transistor (HEMT) that amplifies and outputs an analog measurement signal in real time according to the state change of the qubit from the semiconductor quantum dot array; An analog Computing-In-Memory (CIM) based neural network processing unit (NPU) that directly receives the analog measurement signal output from the above-mentioned low-temperature amplifier without analog-to-digital conversion (ADC), performs matrix multiplication (MAC) operations based on analog voltage or current in batches within a memory cell array to calculate a correction value for quantum error correction; and A control unit comprising, based on the correction value calculated by the above NPU, a gate control voltage of the next operation cycle applied to the first electrode layer or the second electrode layer in real time, Analog feedback control-based semiconductor quantum computing device.
  2. In paragraph 1, The semiconductor quantum dot array and the analog CIM-based NPU are packaged in a three-dimensional (3D) stacked package based on the same silicon, and Data transmission and reception between the above qubit array and the above NPU is characterized by being performed through an ultra-high-speed parallel data bus based on a vertical through-silicon via (TSV) penetrating the above three-dimensional stacked structure. Analog feedback control-based semiconductor quantum computing device.
  3. In paragraph 1, An analog-to-digital converter is not interposed between the above-mentioned low-temperature amplifier and the above-mentioned analog CIM-based NPU, and The above-mentioned low-temperature amplifier includes a level shifter that clamps the analog measurement signal within a predetermined voltage range (Vmin ~ Vmax), and Characterized that the output analog voltage of the above level shifter is applied as a direct input voltage to the memory cell array of the above NPU. Analog feedback control-based semiconductor quantum computing device.
  4. In paragraph 3, The above-mentioned low-temperature amplifier includes a plurality of channels of HEMT amplifier circuits corresponding to each of the plurality of quantum dots, and The level shifter outputs of the above multiple channels are applied simultaneously in parallel to each row of the memory cell array of the NPU, characterized in that the state information of multiple qubits is processed collectively within a single cycle. Analog feedback control-based semiconductor quantum computing device.
  5. In paragraph 1, The memory cell array of the analog CIM-based NPU above is, It includes a resistive random-access memory (ReRAM) or phase-change memory (PCM) device, The matrix multiplication operation in the memory cell array is characterized by being performed using an Ohm's Law-based current summing method in which the conductivity value of each memory cell represents the weight of the neural network, and the current corresponding to the product of the input voltage and the conductivity is summed in the column direction. Analog feedback control-based semiconductor quantum computing device.
  6. In paragraph 1, The memory cell array of the above analog CIM-based NPU includes a 6T cell array based on static random access memory (SRAM), and The matrix multiplication operation in the above 6T cell array is characterized by being performed using a partial summation method that outputs an analog accumulated value by partially summing the output current based on the digital weight bits stored in the SRAM cell. Analog feedback control-based semiconductor quantum computing device.
  7. In paragraph 1, The above control unit is, A digital-to-analog converter (DAC) that converts a correction value calculated by the above NPU into a digital signal; and Characterized by including a gate driver that receives the output voltage of the above DAC and generates a control voltage to be applied to a barrier gate or plunger gate of the above multilayer gate bank structure. Analog feedback control-based semiconductor quantum computing device.
  8. In paragraph 1, The above analog CIM-based NPU is, Implementing a neural network with a Multi-Layer Perceptron (MLP) structure including an input layer, one or more hidden layers, and an output layer, The above neural network operates as a pre-trained quantum error syndrome classifier using qubit state measurement data of the semiconductor quantum dot array as training data, and The above output layer is characterized by outputting an increment (ΔV) of the correction gate voltage for each qubit in parallel. Analog feedback control-based semiconductor quantum computing device.
  9. In paragraph 1, The above semiconductor quantum dot array operates in a cryogenic environment of 4K (Kelvin) or lower, and The analog CIM-based NPU is placed in the same cryogenic environment as the semiconductor quantum dot array, or in an intermediate temperature environment of greater than 4K and less than or equal to 300K, and is electrically connected to the semiconductor quantum dot array through the low-temperature amplifier. The above analog CIM-based NPU is characterized by being manufactured using a CMOS process or an FD-SOI (Fully Depleted Silicon-On-Insulator) process having cryogenic operating characteristics. Analog feedback control-based semiconductor quantum computing device.

Description

Analog feedback control-based semiconductor quantum computing device The present invention relates to a semiconductor spin qubit-based quantum computing device, and more specifically, to an ultra-low latency quantum computing device that completes an error correction loop within the qubit coherence time by directly inputting a state measurement signal of a qubit to an analog Computing-In-Memory (CIM) based neural network processing unit (NPU) without analog-to-digital conversion (ADC) and feeding back the output correction value of the NPU to the gate voltage in real time. Quantum computing is a next-generation computational paradigm that utilizes the superposition and entanglement properties of qubits to efficiently solve problems that require exponential time for classical computers. Among these, the semiconductor spin qubit method captures a single electron in a silicon (Si) or silicon-germanium (Si/Ge) based quantum dot (QD) and utilizes the electron's spin state (spin-up ↑ or spin-down ↓) as the basic unit of quantum information. This method is recognized for its high potential compared to the superconducting qubit method in terms of large-scale integration and mass production capabilities, due to its high compatibility with existing silicon semiconductor processes. However, semiconductor spin qubit systems are vulnerable to various error sources, such as environmental noise, charge noise, and nuclear spin noise, and the coherence time (T2*), which is the time during which a qubit's quantum state remains valid, is generally only tens to hundreds of microseconds. If the Quantum Error Correction (QEC) loop, which detects and corrects errors, is not completed within such a short coherence time, the reliability of the computation results is fundamentally degraded. The error correction loop of a quantum computing system according to conventional technology proceeds in the order of qubit state measurement → HEMT (High Electron Mobility Transistor)-based cryogenic amplification → analog-to-digital converter (ADC) → digital processor (FPGA or GPU)-based error correction algorithm computation → digital-to-analog converter (DAC) → qubit gate voltage correction. In this structure, the ADC generates a conversion delay of tens of nanoseconds to several microseconds during the process of converting the analog measurement signal into a digital codeword, and the subsequent matrix operation and decoding process in the digital processor accumulates additional processing delays. Furthermore, a thermal boundary exists between the qubit control circuit operating in a cryogenic environment (below 4K) and the digital processor operating at room temperature, and wiring crossing this boundary simultaneously causes signal transmission delay and heat load. Consequently, conventional feedback structures including ADCs encroach upon the qubit coherence time, acting as a fundamental technical barrier that hinders the implementation of high-reliability quantum computation. To address these issues, it is necessary to introduce a Computing-In-Memory (CIM)-based analog NPU capable of performing neural network inference directly within the analog domain by omitting the ADC conversion process. A CIM-based analog NPU utilizes the electrical characteristics (such as conductivity) of the memory cells themselves as neural network weights and is structured to complete Multiply-Accumulate (MAC) operations in a single cycle by physically summing the currents corresponding to the product of the input voltage and conductivity. However, conventionally, no technology has been disclosed that applies such an analog CIM NPU to the error correction loop of a semiconductor quantum dot array to construct a fully analog feedback loop without an ADC. FIG. 1 is a system comparison block diagram illustrating a comparison between an ADC-included feedback loop according to the prior art and an ADC-free analog feedback loop according to the present invention. FIG. 2 is a block diagram illustrating the overall system architecture of a semiconductor quantum computing device based on analog feedback control according to one embodiment of the present invention. FIG. 3 is a cross-sectional view illustrating the cross-sectional structure of a semiconductor quantum dot array (100) according to one embodiment of the present invention. FIG. 4 is a plan view and a cross-sectional view of a multilayer gate bank structure according to one embodiment of the present invention. FIG. 5 is a circuit diagram of a HEMT-based low-temperature amplifier (200) according to one embodiment of the present invention, including a multi-channel parallel configuration and a level shifter (220). FIG. 6 is a structural diagram illustrating the internal structure of an analog CIM-based NPU (300) according to one embodiment of the present invention, including a matrix arrangement of memory cell arrays (310), an input voltage application direction, and a current summing direction. FIG. 7 is a pr