KR-20260067408-A - SEMICONDUCTOR DEVICE

Abstract

The semiconductor device of the present disclosure comprises a substrate having a first region and a second region arranged in a first direction, a peripheral circuit structure including circuit elements arranged on the substrate, and a cell structure arranged on the peripheral circuit structure, wherein the cell structure may include a mold structure in which a mold insulating layer and a gate electrode are alternately stacked, a channel structure penetrating the mold structure in the first region, a contact structure in which the gate electrode is in contact in the second region, an upper wiring extending in a second direction intersecting the first direction on the mold structure and spaced apart from each other along the first direction, and a marker pattern overlapping the upper wiring in a third direction intersecting the first direction and the second direction.

Inventors

• 박병곤
• 박준범
• 신용준
• 오수식
• 오현석
• 윤태수
• 이수영

Assignees

• 삼성전자주식회사

Dates

Publication Date

20260513

Application Date

20241104

Claims (20)

1. A peripheral circuit structure comprising a substrate having a first region and a second region arranged in a first direction and circuit elements arranged on said substrate; and It includes a cell structure disposed on the above peripheral circuit structure, and The above cell structure is, A mold structure in which mold insulating layers and gate electrodes are alternately stacked; A channel structure penetrating the mold structure in the first region; A contact structure in contact with the gate electrode in the second region above; Upper wiring extending in a second direction intersecting the first direction on the mold structure and spaced apart from each other along the first direction; and A semiconductor device comprising a marker pattern that overlaps with the upper wiring in a third direction intersecting the first direction and the second direction.
2. In Article 1, A semiconductor device in which the above marker pattern overlaps with the above upper wiring in the first direction and the second direction.
3. In Article 2, A semiconductor device in which the upper surface of the above marker pattern is located at the same level as the upper surface of the above upper wiring.
4. In Article 2, A semiconductor device in which the width in the first direction of the upper surface of the marker pattern is greater than the width in the first direction of the lower surface of the marker pattern.
5. In Article 1, The above upper wiring includes a first upper wiring and a second upper wiring spaced apart from the first upper wiring in the first direction, and The above marker pattern is, A first unit pattern comprising a first marker overlapping the first upper wiring and the third direction, and a second marker overlapping the second upper wiring and the third direction and positioned staggered with the first marker in the first direction; and A semiconductor device comprising a second unit pattern including a third marker overlapping the first marker in the first direction and a fourth marker overlapping the second marker in the first direction.
6. In Article 5, A semiconductor device in which the first unit pattern and the second unit pattern are repeated in the first direction or the second direction.
7. In Article 5, A semiconductor device comprising, wherein the marker pattern further comprises an extended marker pattern that overlaps with at least a portion of the first unit pattern or the second unit pattern in the first direction and is disposed in the second region.
8. In Article 7, The first unit pattern includes a first reference marker located at one end and a second reference marker located at the other end based on the second direction, and The above extended marker pattern is, A first extension marker that overlaps the first reference marker and the first direction; A second extension marker overlapping the second reference marker and the first direction; and A semiconductor device comprising a third extension marker located midway between the first extension marker and the second extension marker based on the second direction.
9. In Article 1, It further includes a plurality of wordline cutting structures that extend along the first direction in the first region and the second region and partition each of the plurality of cell blocks, and A semiconductor device in which at least a portion of the above marker pattern overlaps with the wordline cutting structure in the third direction.
10. In Article 5, A semiconductor device in which, from a planar perspective, the marker pattern includes a zigzag pattern.
11. In Article 1, It further includes an interlayer insulating film positioned at a higher level than the upper wiring above, and A semiconductor device in which the above marker pattern overlaps the above interlayer insulating film in the first direction and the second direction.
12. In Article 11, The above marker pattern is a semiconductor device comprising a metal material.
13. In Article 1, The above peripheral circuit structure includes a first bonding pad electrically connected to the channel structure, and A semiconductor device comprising a second bonding pad in contact with the first bonding pad, wherein the cell structure above includes the first bonding pad.
14. In Article 13, A plate layer disposed on the upper surface of the mold structure, comprising a first surface facing the peripheral circuit structure and a second surface facing in the opposite direction to the first surface; and It further includes via structures spaced apart from each other along the first direction on the second surface of the plate layer, and A semiconductor device in which the upper wiring is disposed on the upper surface of the via structure.
15. A peripheral circuit structure comprising a substrate having a first region and a second region arranged side by side in a first direction and circuit elements arranged on said substrate; and It includes a cell structure disposed on the above peripheral circuit structure, and The above cell structure is, A mold structure in which mold insulating layers and gate electrodes are alternately stacked; A channel structure penetrating the mold structure in the first region; A contact structure in contact with the gate electrode in the second region above; Upper wiring comprising cell upper wiring disposed on the first region and extended upper wiring disposed on the second region, extending in a second direction intersecting the first direction and spaced apart from each other along the first direction; and A marker pattern including a cell marker pattern overlapping with the cell upper wiring in a third direction intersecting the first direction and the second direction, and an extension marker pattern overlapping with the extension upper wiring, A semiconductor device in which the above-mentioned extension marker pattern overlaps with at least a portion of the above-mentioned cell marker pattern in the first direction.
16. In Article 15, A semiconductor device comprising an insulating material, wherein the above marker pattern overlaps the above upper wiring in the first direction and the second direction.
17. In Article 16, A semiconductor device in which the cell marker pattern is arranged to overlap each of the upper wires adjacent to each other among the plurality of upper wires in the second direction.
18. In Article 15, A semiconductor device in which each of the plurality of markers constituting the above marker pattern has a length in the second direction longer than the length in the first direction.
19. In Article 15, A semiconductor device in which the length in the first direction of the above-mentioned extended upper wiring is longer than the length in the first direction of the above-mentioned cell upper wiring.
20. Main board; A semiconductor device comprising a peripheral circuit structure and a cell structure stacked on the peripheral circuit structure on the main substrate; and On the main board above, a controller electrically connected to the semiconductor device is included, and The above cell structure is, A mold structure having a plurality of mold insulating layers extending in a first direction and a plurality of gate electrodes alternately stacked; A channel structure penetrating the mold structure in the first region; A contact structure in contact with the gate electrode in the second region; Upper wiring including cell upper wiring disposed on the first region and extended upper wiring disposed on the second region, extending in a second direction intersecting the first direction and spaced apart from each other along the first direction; and A marker pattern including a cell marker pattern overlapping with the cell upper wiring in a third direction intersecting the first direction and the second direction, and an extension marker pattern overlapping with the extension upper wiring, An electronic system in which the above-mentioned extension marker pattern overlaps with at least a portion of the above-mentioned cell marker pattern in the first direction.

Description

Semiconductor Device The present disclosure relates to a semiconductor device. Semiconductor devices are core components used to control or amplify electrical signals in electronic devices, and various types of semiconductor devices can be manufactured. Semiconductor devices can be produced by forming various microstructures on a semiconductor wafer through multiple unit processes, such as etching, deposition, or ion implantation. Furthermore, it is necessary to analyze whether defects occur and the locations of defects after the semiconductor device is manufactured. To analyze defects in semiconductor devices, the devices can be observed using optical equipment such as electron microscopes. In particular, to quickly identify the location of defects, the location of the defects can be determined relatively by using a portion of the semiconductor device's numerous structures as a reference. FIG. 1 is a plan view illustrating a semiconductor device according to one embodiment of the present disclosure. Figure 2 is a cross-sectional view showing a cross-section cut along the X-X' line of Figure 1. Figure 3 is an enlarged view of part A of Figure 1. Figures 4 and 5 are enlarged views of section B of Figure 2. FIG. 6 is a drawing for illustrating a marker pattern according to one embodiment of the present disclosure. FIGS. 7 to 10 are plan views illustrating a semiconductor device including a marker pattern according to various embodiments of the present disclosure. FIG. 11 is a plan view illustrating a semiconductor device including a marker pattern according to one embodiment of the present disclosure. FIGS. 12 to 16 are intermediate step drawings for explaining a method of manufacturing a semiconductor device according to one embodiment of the present disclosure. FIG. 17 is a plan view illustrating a semiconductor device including a marker pattern according to one embodiment of the present disclosure. FIGS. 18 to 22 are intermediate step drawings for explaining a method of manufacturing a semiconductor device according to one embodiment of the present disclosure. FIG. 23 is a plan view illustrating a semiconductor device including a marker pattern according to one embodiment of the present disclosure. FIG. 24 is an exemplary block diagram for illustrating an electronic system according to some embodiments of the present disclosure. FIG. 25 is an exemplary perspective view for illustrating an electronic system according to some embodiments of the present disclosure. FIG. 26 is a schematic cross-sectional view cut along the VV line of FIG. 25. A semiconductor device according to some embodiments of the present disclosure will be described in detail below with reference to the drawings. FIG. 1 is a plan view illustrating a semiconductor device according to one embodiment of the present disclosure. FIG. 2 is a cross-sectional view illustrating a section cut along the line X-X' of FIG. 1. FIG. 3 is an enlarged view illustrating portion A of FIG. 1. FIG. 4 and FIG. 5 are enlarged views illustrating portion B of FIG. 2. Referring to FIGS. 1 and FIGS. 2, a semiconductor device according to one embodiment of the present disclosure may include a first region (R1) and a second region (R2). The first region (R1) may be a region where a memory cell array is placed. The memory cell array may include a plurality of memory cell blocks (BLK). Each memory cell block (BLK) may include a plurality of memory cells. Each memory cell block (BLK) may extend in a first direction (D1). Each memory cell block (BLK) may be partitioned from one another by a wordline cutting structure (WLC). The second area (R2) may be an extension area and a penetration area. For example, a contact structure (WCS), a source contact structure (SCS), an input/output contact structure (ICS), etc. may be placed on the second area (R2). The first region (R1) and the second region (R2) may be arranged side by side in the first direction (D1). However, not limited thereto, the second region (R2) may be arranged in a form that surrounds the first region (R1). Memory cell blocks (BLK) can form a cell block structure (BKS). For example, a first cell block structure (BKS_1) and a second cell block structure (BKS_2) are illustrated in FIG. 1. The first cell block structure (BKS_1) and the second cell block structure (BKS_2) are each illustrated as being composed of 11 memory cell blocks (BLK), but are not limited thereto. A marker pattern (MP) can be formed repeatedly in each of the first cell block structure (BKS_1) and the second cell block structure (BKS_2). That is, the marker pattern (MP) can be repeated identically in each of the first cell block structure (BKS_1) and the second cell block structure (BKS_2). From a planar perspective, each of the word line cutting structures (WLC) may be a connected shape. In some embodiments, the word line cutting structures (WLC) may be spaced apart from each other in a first direction (D1). Each of the word line cutting str