KR-20260067450-A - PROCESSOR, DISPLAY DEVICE HAVING PROCESSOR, AND ELECTRONIC DEVICE HAVING PROCESSOR

KR20260067450AKR 20260067450 AKR20260067450 AKR 20260067450AKR-20260067450-A

Abstract

The present invention provides a display device comprising: a pixel portion including pixels connected to data lines, gate lines and light emission control lines; a data driver that outputs a data voltage through output lines; a data distribution circuit that connects each of the output lines to an odd-numbered data line among a pair of data lines by a first control signal during a first sub-frame period and connects each of the output lines to an even-numbered data line among a pair of data lines by a second control signal during a second sub-frame period; a first gate driver that sequentially outputs a first gate signal to each of the first gate lines among the gate lines during the first sub-frame period; a second gate driver that sequentially outputs a second gate signal to each of the second gate lines among the gate lines during the second sub-frame period; and a light emission control driver that groups the light emission control lines into groups of four and outputs light emission control signals in group units.

Inventors

박세혁

Assignees

삼성디스플레이 주식회사

Dates

Publication Date: 20260513
Application Date: 20241104

Claims (20)

A pixel section including pixels connected to data lines, gate lines, and light emission control lines; A data driver configured to output data voltage through output lines; A data distribution circuit configured to connect each of the output lines to one of a pair of data lines by a first control signal during a first subframe period, and to connect each of the output lines to the other of a pair of data lines by a second control signal during a second subframe period; A first gate driver configured to sequentially output a first gate signal to each of the first gate lines among the gate lines during the first sub-frame period; A second gate driver configured to sequentially output a second gate signal to each of the second gate lines among the gate lines during the second sub-frame period; and A display device comprising: a light emission control driver configured to group the light emission control lines into groups of four and output light emission control signals in group units.
In paragraph 1, A display device configured such that the data distribution circuit connects each of the output lines to an odd-numbered data line among a pair of data lines during the first sub-frame period and connects each of the output lines to an even-numbered data line among a pair of data lines during the second sub-frame period.
In paragraph 2, Pixels connected to the odd-numbered data lines are connected to the first gate lines, and A display device in which pixels connected to the above even-numbered data lines are connected to the above second gate lines.
In paragraph 1, The above data distribution circuit is, During the first subframe period, each of the odd-numbered output lines among the output lines is connected to the odd-numbered data line among the pair of data lines, and each of the even-numbered output lines is connected to the even-numbered data line among the pair of data lines, and A display device configured to connect each of the odd-numbered output lines among the output lines to an even-numbered data line among a pair of data lines during the second sub-frame period, and to connect each of the even-numbered output lines to an odd-numbered data line among a pair of data lines.
In paragraph 1, A display device configured such that the data driver outputs a data voltage synchronized with the output timing of the first control signal during the first sub-frame period and outputs a data voltage synchronized with the output timing of the second control signal during the second sub-frame period.
In paragraph 1, The pixel portion includes first pixels and second pixels that are connected to odd-numbered data lines among the data lines and arranged alternately in a column direction, and third pixels that are connected to even-numbered data lines among the data lines and arranged repeatedly in a column direction. A display device in which the first pixels, the second pixels, and the third pixels emit light of different colors.
In paragraph 6, A display device configured such that the data driver alternately outputs a first color data voltage and a second color data voltage to each of the output lines during the first sub-frame period in synchronization with the output timing of the first gate signal, and outputs a third color data voltage to each of the output lines during the second sub-frame period in synchronization with the output timing of the second gate signal.
In paragraph 6, The above data driver is, During the first subframe period, a first color data voltage and a second color data voltage are alternately output to each of the odd-numbered output lines among the output lines in synchronization with the output timing of the first gate signal, and a third color data voltage is output to each of the even-numbered output lines in synchronization with the output timing of the first gate signal. A display device configured to output the third color data voltage to each of the odd-numbered output lines among the output lines during the second sub-frame period in synchronization with the output timing of the second gate signal, and to alternately output the first color data voltage and the second color data voltage to each of the even-numbered output lines in synchronization with the output timing of the second gate signal.
In paragraph 1, The first gate driver is configured to sequentially output the first gate signal to each of the first gate lines in synchronization with the output timing of the first control signal during the first sub-frame period, and A display device configured such that the second gate driver outputs the second gate signal sequentially to each of the second gate lines in synchronization with the output timing of the second control signal during the second sub-frame period.
In paragraph 1, A display device configured such that the light emission control driver outputs the light emission control signals in synchronization with the output timing of a first light emission control clock signal and a second light emission control clock signal delayed at a predetermined interval from the first light emission control clock signal.
In Paragraph 10, A display device in which the odd-numbered light-emitting control signals among the light-emitting control signals are output in synchronization with the output timing of the first light-emitting control clock signal, and the even-numbered light-emitting control signals among the light-emitting control signals are output in synchronization with the output timing of the second light-emitting control clock signal.
In paragraph 1, A display device configured such that the light-emitting control driver operates once during the first sub-frame period and operates once during the second sub-frame period.
In paragraph 1, The above light emission control driver includes light emission control stages that are dependently connected to one another, and A display device in which each of the above-mentioned light emission control stages is connected to four of the above-mentioned light emission control lines and configured to simultaneously supply the light emission control signals.
A pixel section comprising first pixels and second pixels connected to a first data line and arranged alternately in a column direction, and third pixels connected to a second data line; A data driver configured to output data voltage through output lines; A data distribution circuit configured to connect a first output line among the output lines to the first data line by a first control signal, and to connect the first output line to the second data line by a second control signal; A first gate driver configured to output first gate signals to the first pixels and the second pixels through the first gate lines; A second gate driver configured to output second gate signals to the third pixels through the second gate lines; and A light emission control driver configured to output light emission control signals to the first pixels, the second pixels, and the third pixels through light emission control lines; A display device in which the ON voltage period of each of the above-mentioned light emission control signals overlaps with the ON voltage period of four consecutive first gate signals or the ON voltage period of four consecutive second gate signals.
In Paragraph 14, A display device configured such that the light emission control driver groups the light emission control lines into groups of four and outputs light emission control signals sequentially in group units.
In Paragraph 14, One frame includes a first subframe period and a second subframe period, and During the first subframe period, the first control signal repeatedly outputs an on voltage and an off voltage, and the second control signal maintains an off voltage. A display device in which the first control signal maintains an off voltage during the second subframe period, and the first control signal repeatedly outputs an on voltage and an off voltage.
In Paragraph 16, A display device configured such that the data driver outputs a data voltage synchronized with the output timing of the first gate signal during the first sub-frame period and outputs a data voltage synchronized with the output timing of the second gate signal during the second sub-frame period.
In Paragraph 16, The first pixels emit light in a first color, the second pixels emit light in a second color, and the third pixels emit light in a third color. A display device in which the data driver alternately outputs a first color data voltage and a second color data voltage to each of the output lines during the first sub-frame period, and repeatedly outputs a third color data voltage to each of the output lines during the second sub-frame period.
In Paragraph 14, The first gate driver is configured to output the first gate signal in synchronization with the output timing of the first control signal, and A display device configured such that the second gate driver outputs the second gate signal in synchronization with the output timing of the second control signal.
In Paragraph 14, A display device configured such that the light emission control driver outputs the light emission control signals in synchronization with a first light emission control clock signal and a second light emission control clock signal delayed at a predetermined interval from the first light emission control clock signal.

Description

Processor, display device having a processor, and electronic device having a processor The present invention relates to a processor, a display device including a processor, and an electronic device including a processor. A display device is equipped with a number of gate lines, a number of data lines, and a number of pixels located at the intersections thereof. In order to apply a data voltage to each of the data lines, the data driver must be equipped with a number of output lines corresponding to the number of data lines, and there is a problem that manufacturing costs increase as a number of integrated circuits are required. FIGS. 1a and FIGS. 1b are each plan views schematically illustrating a display device according to one embodiment of the present invention. FIG. 2 is a schematic diagram showing a display device according to one embodiment of the present invention. FIGS. 3a and FIGS. 3b are each equivalent circuit diagrams schematically showing a pixel according to one embodiment of the present invention. FIG. 4a is a diagram for schematically explaining the operation of a pixel unit and a data distribution circuit according to an embodiment of the present invention. FIG. 4b is a timing diagram for schematically explaining the operation of the display device shown in FIG. 4a. FIG. 5a is a diagram for explaining the data voltage applied to the output line during the first subframe period of the display device shown in FIG. 4a, and FIG. 5b is a diagram for explaining the data voltage applied to the output line during the second subframe period of the display device shown in FIG. 4a. FIG. 6a is a diagram for schematically explaining the operation of a pixel unit and a data distribution circuit according to another embodiment of the present invention. FIG. 6b is a timing diagram for schematically explaining the operation of the display device shown in FIG. 6a. FIG. 7 is a schematic diagram showing a display device according to one embodiment of the present invention. FIG. 8 is a timing diagram for schematically explaining the operation of the display device shown in FIG. 7. FIG. 9 is a schematic diagram showing an electronic device according to one embodiment of the present invention. FIG. 10 is a drawing for explaining a driver IC according to one embodiment of the present invention. FIGS. 11a and FIGS. 11b are each diagrams for schematically illustrating the operation of a driver IC according to an embodiment of the present invention. The present invention is capable of various modifications and may have various embodiments; specific embodiments are illustrated in the drawings and described in detail in the detailed description. The effects and features of the present invention, and the methods for achieving them, will become clear by referring to the embodiments described below in detail together with the drawings. However, the present invention is not limited to the embodiments disclosed below but can be implemented in various forms. Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. When describing with reference to the drawings, identical or corresponding components are given the same reference numerals, and redundant descriptions thereof will be omitted. In this specification, terms such as first, second, etc. are used not in a limiting sense, but for the purpose of distinguishing one component from another. In this specification, singular expressions include plural expressions unless the context clearly indicates otherwise. In this specification, terms such as "include" or "have" mean that the features or components described in the specification exist, and do not preclude the possibility that one or more other features or components may be added. In this specification, when a part such as a film, region, or component is described as being on or above another part, it includes not only cases where it is immediately above the other part, but also cases where another film, region, or component is interposed therein. In this specification, when it is stated that a membrane, region, component, etc. is connected, it includes cases where the membrane, region, or component is directly connected, or/or cases where other membranes, regions, or components are interposed between them to form an indirect connection. For example, when it is stated that a membrane, region, or component, etc. is electrically connected in this specification, it indicates cases where the membrane, region, or component, etc. are directly electrically connected, and/or cases where other membranes, regions, or components are interposed between them to form an indirect electrical connection. In this specification, "A and/or B" indicates the case where it is A, B, or both A and B. And, "at least one of A and B" indicates the case where it is A, B, or both A and B. In this specification, the x direction, y direction, and z direction are not limited to directions along