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KR-20260067453-A - DISPLAY PIXEL CIRCUIT AND MANUFACTURING METHOD THEREOF

KR20260067453AKR 20260067453 AKR20260067453 AKR 20260067453AKR-20260067453-A

Abstract

One embodiment of the present invention discloses a method for manufacturing a thin-film transistor in a display pixel circuit, comprising the steps of forming a gate electrode, forming a gate insulating layer comprising a ferroelectric material on the gate electrode, forming a capping layer comprising a semiconductor layer comprising an oxide semiconductor and a metal layer on the semiconductor layer on the gate insulating layer, expressing ferroelectricity of the gate insulating layer through a first heat treatment process, and patterning the metal layer to form a source-drain electrode.

Inventors

  • 김태상
  • 김현재
  • 박준석
  • 한재성

Assignees

  • 삼성디스플레이 주식회사
  • 연세대학교 산학협력단

Dates

Publication Date
20260513
Application Date
20241105

Claims (20)

  1. A method for manufacturing a display pixel circuit comprising a switching thin-film transistor, a driving thin-film transistor connected to the switching thin-film transistor, and a light-emitting element connected to the driving thin-film transistor, wherein Step of forming the above driving thin-film transistor; and A step of forming a light-emitting element connected to the above-mentioned driving thin-film transistor; Includes, The step of forming the above-mentioned driving thin-film transistor is, Step of forming a gate electrode; A step of forming a gate insulating layer containing a ferroelectric material on the gate electrode; A step of forming a semiconductor layer comprising an oxide semiconductor and a capping layer comprising a metal layer on the semiconductor layer on the gate insulating layer; A step of expressing ferroelectricity of the gate insulating layer through a first heat treatment process; and A step of forming a source-drain electrode by patterning the above metal layer; A method including
  2. In paragraph 1, After the step of forming the above source-drain electrode A step of patterning the semiconductor layer and activating the semiconductor layer through a second heat treatment process; A method that further includes.
  3. In paragraph 2, The steps of forming the source-drain electrode and patterning the semiconductor layer are: A method performed using a halftone mask.
  4. In paragraph 1, Prior to the step of forming the metal layer above, The method further includes the step of patterning the semiconductor layer, After the step of forming the above source-drain electrode, A step of activating the semiconductor layer through a second heat treatment process; A method that further includes.
  5. In paragraph 2 or 4, The above first heat treatment process is performed at a first temperature for a first time interval, and A method in which the above secondary heat treatment process is performed at a second temperature lower than the first temperature for a second time interval longer than the first time interval.
  6. In paragraph 1, The above ferroelectric material is hafnium zirconium oxide (HZO) and A method in which the gate electrode and the metal layer are made of a material having a coefficient of thermal expansion smaller than that of the ferroelectric material.
  7. In paragraph 1, A method in which the gate insulating layer is formed using one or more deposition methods selected from the group consisting of atomic layer deposition, sputtering deposition, and spin coating deposition.
  8. In paragraph 1, A method in which the oxide semiconductor comprises one or more materials selected from the group consisting of IGO (InGaO), IZO (InZnO), ITZO (InSnZnO), and IGZO (InGaZnO).
  9. In paragraph 1, A method in which the thickness of the semiconductor layer is within the range of 5 nm to 50 nm.
  10. In paragraph 1, A method in which the thickness of the gate insulating layer is within the range of 10 nm to 20 nm.
  11. In paragraph 1, After the step of forming the gate insulating layer above, A step of forming an additional gate insulating layer between the gate insulating layer and the semiconductor layer, comprising a dielectric material having a wider bandgap than the ferroelectric material; A method that further includes.
  12. In Paragraph 11, A method in which the additional gate insulating layer comprises one or more materials selected from the group consisting of silicon dioxide ( SiO₂ ) and aluminum oxide ( Al₂O₃ ).
  13. In paragraph 1, A method in which the gate electrode and the metal layer comprise one or more materials selected from the group consisting of tungsten (W), platinum (Pt), molybdenum (Mo) and titanium nitride (TiN).
  14. A display pixel circuit comprising a switching thin-film transistor, a driving thin-film transistor connected to the switching thin-film transistor, and a light-emitting element connected to the driving thin-film transistor, The above driving thin-film transistor is Gate electrode; A semiconductor layer including an oxide semiconductor; A gate insulating layer provided between the gate electrode and the semiconductor layer and comprising a ferroelectric material; and Source-drain electrodes formed on the semiconductor layer above; Includes The above ferroelectric material is hafnium zirconium oxide (HZO) and A pixel circuit in which the gate electrode and the source-drain electrode are made of a material having a coefficient of thermal expansion smaller than that of the ferroelectric material.
  15. In Paragraph 14, The above oxide semiconductor comprises one or more materials selected from the group consisting of IGO (InGaO), IZO (InZnO), ITZO (InSnZnO), and IGZO (InGaZnO), forming a pixel circuit.
  16. In Paragraph 14, A pixel circuit having a semiconductor layer thickness within the range of 5 nm to 50 nm.
  17. In Paragraph 14, A pixel circuit having a gate insulating layer thickness within the range of 10 nm to 20 nm.
  18. In Paragraph 14, An additional gate insulating layer comprising a dielectric material having a wider bandgap than the ferroelectric material between the gate insulating layer and the semiconductor layer; A pixel circuit including additionally.
  19. In Paragraph 18, A pixel circuit , wherein the additional gate insulating layer comprises one or more materials selected from the group consisting of silicon dioxide ( SiO₂ ) and aluminum oxide ( Al₂O₃ ).
  20. In Paragraph 14, A pixel circuit comprising one or more materials selected from the group consisting of tungsten (W), platinum (Pt), molybdenum (Mo) and titanium nitride (TiN), wherein the gate electrode and the source-drain electrode comprise the above-mentioned gate electrode and the above-mentioned source-drain electrode.

Description

Display pixel circuit and manufacturing method thereof Embodiments of the present invention relate to a display pixel circuit and a method for manufacturing the same. Generally, in display devices such as organic light-emitting display devices, transistors, connecting electrodes, and wiring are placed in each subpixel to control the brightness of each subpixel. Figure 1 is a block diagram schematically illustrating a display device. Figure 2 is a circuit diagram illustrating an example of the subpixel shown in Figure 1. FIG. 3 is a plan view illustrating an example of the subpixel of FIG. 2. FIGS. 4a to 4h are cross-sectional views illustrating a method for manufacturing a display device according to an embodiment of the present invention. FIGS. 5a to 5c are cross-sectional views illustrating a method for manufacturing a display device according to another embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a display device according to another embodiment of the present invention. FIGS. 7 and 8 are conceptual diagrams illustrating the operating principle of a thin-film transistor included in a display pixel circuit according to an embodiment of the present invention. FIG. 9 is a conceptual diagram showing the experimental results of testing the gate insulation layer characteristics of a thin-film transistor included in a display pixel circuit according to an embodiment of the present invention through a comparative example. FIG. 10 is a conceptual diagram showing experimental results of testing the semiconductor layer characteristics of a thin-film transistor included in a display pixel circuit according to an embodiment of the present invention through a comparative example. FIG. 11 is a conceptual diagram showing experimental results obtained by testing the device characteristics of a thin-film transistor included in a display pixel circuit according to an embodiment of the present invention through a comparative example. The present invention is capable of various modifications and may have various embodiments; specific embodiments are illustrated in the drawings and described in detail in the detailed description. The effects and features of the present invention, and the methods for achieving them, will become clear by referring to the embodiments described below in detail together with the drawings. However, the present invention is not limited to the embodiments disclosed below but can be implemented in various forms. In the following embodiments, terms such as first, second, etc. are used not in a limiting sense, but for the purpose of distinguishing one component from another component. In the following examples, singular expressions include plural expressions unless the context clearly indicates otherwise. In the following embodiments, terms such as "include" or "have" mean that the features or components described in the specification are present, and do not preclude the possibility that one or more other features or components may be added. In the following embodiments, when a part such as a unit, area, or component is described as being on or above another part, it includes not only cases where it is directly on top of another part, but also cases where another unit, area, or component is interposed in between. In the following embodiments, terms such as "connect" or "combine" do not necessarily imply a direct and/or fixed connection or combination of two members unless the context clearly indicates otherwise, nor do they exclude the interposition of another member between the two members. In the drawings, the size of components may be exaggerated or reduced for convenience of explanation. For example, the size and/or thickness of each component shown in the drawings are arbitrarily depicted for convenience of explanation, and therefore the present invention is not necessarily limited to what is illustrated. In the following embodiments, when various components such as layers, films, regions, and plates are described as being "on" another component, this includes not only cases where they are "directly on" another component, but also cases where other components are interposed between them. Furthermore, for convenience of explanation, the size of components in the drawings may be exaggerated or reduced. For example, the size and thickness of each component shown in the drawings are depicted arbitrarily for convenience of explanation, so the present invention is not necessarily limited to what is illustrated. In the following embodiments, the x-axis, y-axis, and z-axis are not limited to three axes in an orthogonal coordinate system and can be interpreted in a broader sense that includes them. For example, the x-axis, y-axis, and z-axis may be orthogonal to each other, but they may also refer to different directions that are not orthogonal to each other. Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the at