KR-20260067457-A - SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME

KR20260067457AKR 20260067457 AKR20260067457 AKR 20260067457AKR-20260067457-A

Abstract

One embodiment of the present invention comprises: a redistribution structure including a redistribution layer; chip structures stacked vertically on the redistribution structure, each including a first surface facing the redistribution structure and a second surface opposite to the first surface; an interconnection structure disposed between the chip structures and including a connecting layer; a mold layer covering at least a portion of each of the chip structures; and posts disposed within the mold layer and electrically connecting the connecting layer and the redistribution layer. The semiconductor package comprises connection bumps disposed below the rewiring structure, wherein each of the chip structures comprises a front end and a back end positioned opposite each other in a first direction, side ends positioned opposite each other in a second direction intersecting the first direction, and connection pads arranged adjacent to the front end and electrically connected to the connection layer and the rewiring layer, a gap-fill layer covering the semiconductor chips and defining the first surface of the chip structure, and pillars disposed within the gap-fill layer and extending from the connection pads to the first surface, wherein the width from the front end to the back end of each of the semiconductor chips is different.

Inventors

김종윤
배명한
배민준
이민영

Assignees

삼성전자주식회사

Dates

Publication Date: 20260513
Application Date: 20241105

Claims (10)

A redistribution structure including a redistribution layer; Chip structures stacked vertically on the above-mentioned redistribution structure, each comprising a first surface facing the above-mentioned redistribution structure and a second surface opposite to the first surface; An interconnection structure disposed between the above chip structures and including a connection layer; A mold layer covering at least a portion of each of the above chip structures; Posts disposed within the above mold layer and electrically connecting the connection layer and the redistribution layer; and It includes connecting bumps positioned below the above-mentioned redistribution structure, and Each of the above chip structures is, Semiconductor chips comprising a front end and a back end positioned opposite each other in a first direction, side ends positioned opposite each other in a second direction intersecting the first direction, and connection pads arranged adjacent to the front end and electrically connected to the connection layer and the redistribution layer, A gap-fill layer covering the semiconductor chips and defining the first surface of the chip structure, and It includes pillars disposed within the gap fill layer and extending from the connection pads to the first surface, The width from the front end to the rear end of each of the above semiconductor chips is different for the semiconductor package.
In Article 1, The above chip structures further include a first side adjacent to the front end, a second side adjacent to the rear end, a third side adjacent to the first side end among the side ends, and a fourth side adjacent to the second side end among the side ends, The first side, the second side, the third side, and the fourth side are a semiconductor package defined by at least one of the front end, the rear end, and the side end of the semiconductor chips and the side portion of the gap fill layer.
In Article 2, The rear end of each of the above semiconductor chips is a semiconductor package aligned with the second side of the corresponding chip structure.
In Article 1, The largest width among the widths of the semiconductor chips is the same as the width in the first direction of the gap fill layer of the semiconductor package.
In Article 1, Each of the above semiconductor chips further includes a lower surface on which the connection pads are arranged and an upper surface opposite to the lower surface, and The above chip structures are a semiconductor package further comprising an attachment film disposed on the upper surface of each of the above semiconductor chips.
A redistribution structure including a redistribution layer; Chip structures stacked vertically on the above-mentioned redistribution structure; An interconnection structure disposed between the above chip structures and including a connection layer; A mold layer surrounding each of the above chip structures; and It includes posts disposed within the mold layer and electrically connected to the redistribution layer and the connection layer, Each of the above chip structures is, A first semiconductor chip comprising first connection pads, wherein the first front surface on which the first connection pads are arranged is positioned to face the rewiring structure, A second semiconductor chip comprising second connection pads, wherein the second front surface on which the second connection pads are arranged faces the rewiring structure, and the second semiconductor chip disposed on the first front surface of the first semiconductor chip. A gap fill layer covering the first front surface and the second front surface, First fillers penetrating the gap fill layer and connected to the first connection pads, and It includes second fillers that penetrate the gap fill layer and are connected to the second connection pads, The above chip structures include a first chip structure on the interconnection structure and a second chip structure between the redistribution structure and the interconnection structure, and A semiconductor package comprising an interconnection structure including an insulating layer between the connecting layer and the first chip structure, and connecting vias penetrating the insulating layer and connecting the connecting layer to the first fillers and the second fillers of the first chip structure.
In Article 6, A semiconductor package in which the height of the first pillars is greater than the height of the second pillars.
In Article 6, The above mold layer includes a first mold layer surrounding the first chip structure and a second mold layer surrounding the second chip structure, and A semiconductor package further comprising an alignment pattern disposed on the first mold layer and the first chip structure, and a cover layer covering the alignment pattern.
A step of forming a cover layer and an alignment pattern on a carrier substrate; A step of attaching a first chip structure to the above cover layer; A step of forming a first mold layer covering the first chip structure; A step of forming an interconnected structure on the first mold layer and the first chip structure; A step of forming posts on the above interconnected structure; A step of attaching a second chip structure to the interconnected structure around the posts; A step of forming a second mold layer covering the above posts and the second chip structure; and The method includes the step of forming a redistribution structure on the second mold layer and the second chip structure, and Each of the above first and second chip structures is, A first semiconductor chip comprising first connection pads, wherein the first front surface on which the first connection pads are arranged faces upward. A second semiconductor chip comprising second connection pads, wherein the second front surface on which the second connection pads are arranged faces upward, the second front surface facing upward. A gap fill layer covering the first front surface and the second front surface, First fillers penetrating the gap fill layer and connected to the first connection pads, and It includes second fillers that penetrate the gap fill layer and are connected to the second connection pads, The above interconnection structure includes a connecting layer that electrically connects the posts to the first and second fillers of the first chip structure, and A method for manufacturing a semiconductor package comprising a redistribution layer electrically connected to the posts and the first and second fillers of the second chip structure, wherein the above redistribution structure is a redistribution layer.
In Article 9, The method further includes the step of forming the first and second chip structures, The step of forming the first and second chip structures is, A step of preparing a semiconductor wafer including a chip region; A step of forming the first fillers within the chip region; A step of attaching the second semiconductor chip having the second fillers formed thereon to the chip region; A step of forming the gap fill layer covering the second semiconductor chip; A step of thinning the semiconductor wafer; and A method for manufacturing a semiconductor package comprising the step of separating the first semiconductor chip corresponding to the chip region from the semiconductor wafer.

Description

Semiconductor Package and Manufacturing Method The present invention relates to a semiconductor package and a method for manufacturing it. As the demand for high capacity, thinness, and miniaturization of electronic products increases, various types of semiconductor packages are being developed. Among these diverse package types, packaging technology that vertically stacks multiple semiconductor chips is being developed. However, as the number of stacked semiconductor chips increases, the risk during the manufacturing process increases, and securing yield becomes difficult. FIG. 1a is a cross-sectional view of a semiconductor package according to an exemplary embodiment, FIG. 1b is a cross-sectional view along line I-I' of FIG. 1a, and FIG. 1c is a cross-sectional view along line II-II' of FIG. 1a. FIG. 2a is a cross-sectional view of a chip structure of an exemplary embodiment, and FIG. 2b is a bottom view of the chip structure of FIG. 2a. FIG. 2c is a cross-sectional view of a chip structure of an exemplary modified example, and FIG. 2d is a bottom view of the chip structure of FIG. 2c. FIG. 3 is a cross-sectional view of a semiconductor package according to an exemplary embodiment. FIG. 4 is a cross-sectional view of a semiconductor package according to an exemplary embodiment. FIG. 5 is a flowchart illustrating a method for manufacturing a chip structure according to an exemplary embodiment. FIGS. 6a to 6f are drawings for explaining the method of manufacturing the chip structure of FIG. 5. FIG. 7 is a flowchart illustrating a method for manufacturing a semiconductor package according to an exemplary embodiment. FIGS. 8a to 8g are drawings for explaining a method of manufacturing a semiconductor package of FIG. 7. Hereinafter, preferred embodiments of the present invention are described as follows with reference to the attached drawings. Unless otherwise specifically stated, terms such as 'upper,' 'upper surface,' 'lower,' 'lower surface,' and 'side surface' in this specification are based on the drawings and may actually vary depending on the direction in which the components are arranged. Additionally, ordinal numbers such as "first," "second," "third," etc., may be used as labels for specific elements, steps, directions, etc., to distinguish various elements, steps, directions, etc. from one another. Terms not described in the specification using "first," "second," etc., may still be referred to as "first" or "second" in the claims. Furthermore, terms referenced by a specific ordinal number (e.g., "first" in a specific claim) may be described elsewhere by a different ordinal number (e.g., "second" in the specification or another claim). FIG. 1a is a cross-sectional view of a semiconductor package (100A) according to an exemplary embodiment, FIG. 1b is a cross-sectional view along line I-I' of FIG. 1a, and FIG. 1c is a cross-sectional view along line II-II' of FIG. 1a. Referring to FIGS. 1a through 1c, a semiconductor package (100A) of an exemplary embodiment may include a rewiring structure (110), chip structures (120), an interconnection structure (130), a mold layer (140), and posts (150). According to an embodiment, the semiconductor package (100A) may further include a cover layer (161) and an alignment pattern (162). A rewiring structure (110) can rewire chip structures (120) to electrically connect them to an external device. The rewiring structure (110) may include an insulating layer (111), a rewiring layer (112), and rewiring vias (113). Connecting bumps (115) may be disposed below the rewiring structure (110). The connecting bumps (115) may be electrically connected to the rewiring layer (112). A semiconductor package (100A) may be connected to an external device, such as a module substrate or a main board, through the connecting bumps (115). The connecting bumps (115) may include, for example, tin (Sn) or an alloy containing tin (Sn-Ag-Cu). In some embodiments, the connecting bumps (115) may have a combined form of a pillar (or underbump metal) and a solder ball. According to an embodiment, a passivation layer (PSV) that protects the redistribution layer (112) and connection bumps (115) from physical and chemical damage may be formed on the lower surface of the redistribution structure (110). The insulating layer (111) may include an insulating resin. The insulating resin may include a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a resin in which inorganic fillers are impregnated into these resins, for example, prepreg, ABF (Ajinomoto Build-up Film), FR-4 (Flame Resistant), BT (Bismaleimide-Triazine). For example, the insulating layer (111) may include a photosensitive resin such as PID (Photo-Imageable Dielectric). The insulating layer (111) may include insulating layers stacked in the vertical direction (D3), but depending on the process, the boundaries between the insulating layers may be indistinct. The redistribution layer (112) may be disposed