KR-20260067561-A - STORAGE DEVICE AND METHOD OF OPERATING STORAGE DEVICE

Abstract

A storage device includes a memory device and a memory controller. The memory controller communicates with the memory device through a channel to control the memory device. The memory device includes a plurality of memory chips that share the channel and each include a transmitting driver and an adaptive body bias generator. A first adaptive body bias generator of a target memory chip selected by the memory controller among the plurality of memory chips applies a different first body bias to a first transmitting driver of the target memory chip in a write mode that receives write data from the memory controller and in a read mode that transmits read data to the memory controller.

Inventors

• 손영훈
• 유진호
• 강경태
• 김상윤
• 변진도
• 최영돈

Assignees

• 삼성전자주식회사

Dates

Publication Date

20260513

Application Date

20241106

Claims (20)

1. memory device; and It includes a memory controller that communicates with the memory device through a channel to control the memory device, and The above memory device It includes a plurality of memory chips that share the above channel, each including a transmission driver and an adaptive body bias generator, and A storage device in which a first adaptive body bias generator of a target memory chip selected by the memory controller among the plurality of memory chips applies different first body biases to a first transmission driver of the target memory chip in a write mode for receiving write data from the memory controller and a read mode for transmitting read data to the memory controller.
2. In claim 1, the first adaptive body bias generator In the above write mode, a reverse body bias is applied to the first transmitting driver, and A storage device characterized by applying a normal body bias to the first transmitting driver in the above read mode.
3. In paragraph 1, A storage device characterized in that the first transmitting driver includes at least one NMOS transistor and at least one PMOS transistor connected to a data transmission line that is included in the channel to transmit the read data and receives the write data.
4. In paragraph 3, the first adaptive body bias generator In the above entry mode, A first bias voltage lower than the ground voltage is applied to the body of the above NMOS transistor, and A storage device characterized by applying a second bias voltage higher than the power supply voltage to the body of the above-mentioned PMOS transistor to apply the reverse body bias to the first transmission driver.
5. In paragraph 3, the first adaptive body bias generator In the above reading mode, A first bias voltage corresponding to the ground voltage is applied to the body of the above NMOS transistor, and A storage device characterized by applying a second bias voltage of the power supply voltage to the body of the above-mentioned PMOS transistor to apply the normal body bias to the first transmitting driver.
6. In paragraph 3, Each of the one or more non-target memory chips among the plurality of memory chips that are not selected by the memory controller further includes an on-die termination (hereinafter 'ODT') circuit connected to the data transmission line, A storage device characterized in that a corresponding adaptive body bias generator for each of the one or more non-target memory chips applies a different second body bias to a corresponding transmission driver based on whether the corresponding ODT circuit is activated.
7. In paragraph 6, Among the above one or more non-target memory chips, the first non-target memory chip in which the corresponding first ODT circuit is activated includes a second adaptive body bias generator and a second transmission driver, and A storage device characterized in that a second non-target memory chip, in which a corresponding first ODT circuit among the above one or more non-target memory chips is disabled, includes a third adaptive body bias generator and a third transmission driver.
8. In Paragraph 7, The second adaptive body bias generator applies a normal body bias to the second transmitting driver, and A storage device characterized by the third adaptive body bias generator applying a reverse body bias to the third transmitting driver.
9. In paragraph 8, The third transmission driver includes at least one NMOS transistor and at least one PMOS transistor connected to the data transmission line, and The above third adaptive body bias generator A first bias voltage lower than the ground voltage is applied to the body of the above NMOS transistor, and A storage device characterized by applying a second bias voltage higher than the power supply voltage to the body of the above-mentioned PMOS transistor to apply the reverse body bias to the third transmission driver.
10. In paragraph 8, The second transmission driver includes at least one NMOS transistor and at least one PMOS transistor connected to the data transmission line, and The above second adaptive body bias generator A first bias voltage corresponding to the ground voltage is applied to the body of the above NMOS transistor, and A storage device characterized by applying a second bias voltage of the power supply voltage to the body of the above-mentioned PMOS transistor to apply the normal body bias to the second transmission driver.
11. In paragraph 6, Each of the above one or more non-target memory chips determines whether to activate a corresponding ODT circuit based on an ODT signal from the memory control, and A storage device characterized in that the corresponding ODT circuit is included in the corresponding transmission driver of each of the one or more non-target memory chips.
12. In claim 1, each of the plurality of memory chips is A memory cell array comprising a plurality of non-volatile memory cells connected to a plurality of word lines and a plurality of bit lines, which store the above-mentioned write data and provide the above-mentioned read data; An on-die termination (hereinafter 'ODT') circuit included in the above channel, which transmits the read data and is connected to a transmission line that receives the write data; and It further includes a control circuit that controls a corresponding adaptive body bias generator based on a command and address from the memory control and controls a corresponding ODT circuit based on an ODT signal from the memory controller. A storage device characterized in that the plurality of memory chips are sequentially stacked on a printed circuit board in a direction perpendicular to the surface of the printed circuit board.
13. In Clause 12, the above control circuit is An address comparator that generates an internal chip enable signal indicating that it is the target memory chip based on the result of comparing a chip address included in the above address and an identifier address identifying each of the memory chips; and A storage device characterized by including a control signal generator that generates an ODT control signal for selectively activating the corresponding ODT circuit based on the above ODT signal.
14. In Clause 13, the above address comparator Based on the fact that the above chip address and the above identifier address match, the internal chip enable signal is activated, and A storage device characterized by disabling the internal chip enable signal based on the fact that the chip address and the identifier address are different.
15. In Paragraph 12, A storage device characterized in that the plurality of memory chips above operate in a chip enable reduction mode in which they commonly receive a chip enable signal and a chip address.
16. In Paragraph 12, The control circuit selectively activates a command/address chip enable signal from the memory controller and an internal chip enable signal indicating that it is the target memory chip based on the command/address, and Generating an ODT control signal that selectively activates the corresponding ODT circuit based on the above ODT signal, and A storage device characterized in that the above command/address includes a LUN address representing an active logical unit number (hereinafter 'LUN').
17. memory device; and It includes a memory controller that communicates with the memory device through a channel to control the memory devices, and The above memory device It includes a plurality of memory chips that share a data bus for transmitting data and each receive chip selection signals from the memory controller. Each of the plurality of memory chips includes a memory cell array connected to a plurality of word lines and a plurality of bit lines to store the data, a transmission driver, and an adaptive body bias generator. A storage device in which a first adaptive body bias generator of a target memory chip selected by one of the chip selection signals among the plurality of memory chips applies different first body biases to a first transmission driver of the target memory chip in a write mode for receiving write data from the memory controller and a read mode for transmitting read data to the memory controller.
18. In paragraph 17, the above-mentioned first adaptive body bias generator In the above write mode, a reverse body bias is applied to the first transmitting driver, and In the above readout mode, a normal body bias is applied to the first transmitting driver, and The first transmission driver includes at least one NMOS transistor and at least one PMOS transistor connected to the data bus, and The above-mentioned first adaptive body bias generator In the above entry mode, A first bias voltage lower than the ground voltage is applied to the body of the above NMOS transistor, and A second bias voltage higher than the power supply voltage is applied to the body of the above PMOS transistor to apply the reverse body bias to the first transmitting driver, and In the above reading mode, A first bias voltage corresponding to the ground voltage is applied to the body of the above NMOS transistor, and A storage device characterized by applying a second bias voltage of the power supply voltage to the body of the above-mentioned PMOS transistor to apply the normal body bias to the first transmitting driver.
19. In Paragraph 17, Each of the one or more non-target memory chips among the plurality of memory chips that are not selected by the chip selection signals further includes an on-die termination (hereinafter 'ODT') circuit connected to the data bus, and A corresponding adaptive body bias generator for each of the one or more non-target memory chips applies a different second body bias to a corresponding transmit driver based on whether the corresponding ODT circuit is enabled, and Among the above one or more non-target memory chips, the first non-target memory chip in which the corresponding first ODT circuit is activated includes a second adaptive body bias generator and a second transmission driver, and A second non-target memory chip in which a corresponding first ODT circuit among the above one or more non-target memory chips is deactivated includes a third adaptive body bias generator and a third transmission driver, and The third adaptive body bias generator applies a reverse body bias to the third transmitting driver, and A storage device characterized by the above-described third adaptive body bias generator applying a normal body bias to the above-described second transmitting driver.
20. A method of operation of a storage device comprising a memory controller that controls the memory device by communicating with the memory device through a memory device and a channel, wherein the memory device comprises a plurality of memory chips sharing the channel, A step of determining whether each of the memory chips is selected as a target memory chip based on the chip address from the memory controller; A step of applying different first body biases to an internal first transmission driver based on whether the first adaptive body bias generator of the first memory chip selected as the target memory chip among the plurality of memory chips is in a write mode or a read mode; and A method of operation of a storage device comprising the step of applying different second body biases to an internal second transmission driver based on whether a second adaptive body bias generator of each of one or more non-target memory chips, excluding the target memory chip among the plurality of memory chips, applies a corresponding on-die termination function.

Description

Storage Device and Method of Operating Storage Device The present invention relates to a semiconductor memory device, and more specifically, to a storage device and a method of operating the storage device. A storage device may include a memory device equipped with a plurality of memory chips and a controller that controls the memory device. Conventionally, communication between the memory device and the controller was performed at a relatively low operating frequency compared to memory systems containing high-speed memory such as DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory). Accordingly, signal integrity between the memory device and the controller and the capacitance of the I/O pads were not critical factors in the overall performance of the storage device. However, recently, high-speed operation of storage devices is required, and consequently, signal integrity and I/O capacitance for reducing channel power have also become critical factors in storage devices to improve the overall performance of computing systems or mobile communication systems. FIG. 1 is a block diagram showing a storage device according to embodiments of the present invention. FIG. 2 is a block diagram showing a memory controller in the storage device of FIG. 1 according to embodiments of the present invention. FIG. 3 shows the connection relationship between the memory controller and the memory device in the storage device of FIG. 1 according to embodiments of the present invention. FIG. 4 is a timing diagram exemplarily illustrating the chip selection operation of the memory device of FIG. 3 according to embodiments of the present invention. FIG. 5 is a block diagram showing the configuration of one of a plurality of memory chips in the memory device of FIG. 3 according to embodiments of the present invention. FIG. 6a shows a data input/output circuit in the memory chip of FIG. 5 according to embodiments of the present invention. FIG. 6b shows the configuration of a transmitting driver in the data input/output circuit of FIG. 6a according to embodiments of the present invention. FIG. 7 is a block diagram showing an adaptive body bias generator in the memory chip of FIG. 5 according to embodiments of the present invention. Figure 8 is a block diagram showing an example of a memory plane in the memory chip of Figure 5. FIG. 9 is a circuit diagram showing one of the memory blocks of FIG. 8 according to embodiments of the present invention. FIG. 10 is a block diagram showing a part of the memory chip of FIG. 5 according to embodiments of the invention. FIG. 11 is a circuit diagram showing an example of a transmission driver in the memory chip of FIG. 10 according to embodiments of the present invention. FIG. 12 shows the storage device of FIG. 3 according to embodiments of the present invention in write mode. FIG. 13 shows the storage device of FIG. 3 according to embodiments of the present invention in read mode. FIG. 14 is a table showing the body bias applied to the transmitting drivers of the memory chips in the storage devices of FIG. 12 and FIG. 13. FIG. 15 is a table showing normal body bias and reverse body bias applied to transistors included in a transmitting driver according to embodiments of the present invention. FIGS. 16 and FIGS. 17 are cross-sectional views showing an NMOS transistor and a PMOS transistor included in the transmitting driver of FIG. 11 according to embodiments of the present invention. FIG. 18 is a block diagram showing the configuration of a control circuit in the memory chip of FIG. 5 according to embodiments of the present invention. FIG. 19 is a block diagram showing a storage device according to embodiments of the present invention. FIG. 20 is a timing diagram exemplarily illustrating the chip selection operation of the memory device of FIG. 19 according to embodiments of the present invention. FIG. 21 is a timing diagram exemplarily illustrating the ODT control operation of the memory device of FIG. 19 according to embodiments of the present invention. FIG. 22 is a block diagram showing a storage device according to embodiments of the present invention. FIG. 23 is a block diagram showing the configuration of one of the memory chips in the storage device of FIG. 22 according to embodiments of the present invention. FIG. 24 shows a first bank array in the memory chip of FIG. 23 according to embodiments of the present invention. FIG. 25 is a block diagram showing an example of a storage device of FIG. 1 according to embodiments of the present invention. FIG. 26 is a flowchart illustrating the operation method of a storage device according to embodiments of the present invention. FIG. 27 is a block diagram showing an electronic system including a semiconductor device according to embodiments of the present invention. Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the attached drawings. Identical components in th