KR-20260067650-A - SEMICONDUCTOR PACKAGE

KR20260067650AKR 20260067650 AKR20260067650 AKR 20260067650AKR-20260067650-A

Abstract

A semiconductor package according to one embodiment of the present invention comprises a package substrate including a plurality of bonding pads, and is mounted on the upper surface of the package substrate and each includes a plurality of pads, wherein the plurality of pads each include a plurality of semiconductor chips including a first data pad to an eighth data pad and a plurality of wires connecting the plurality of pads, wherein the plurality of semiconductor chips include a first semiconductor chip to a fourth semiconductor chip, and the first data pad to the fourth data pad included in the first semiconductor chip and the first data pad to the fourth data pad included in the second semiconductor chip are each connected to each other through first to fourth wires, and the first to fourth wires are separated from the third semiconductor chip and the fourth semiconductor chip.

Inventors

김홍진
정기홍
곽동옥

Assignees

삼성전자주식회사

Dates

Publication Date: 20260513
Application Date: 20241106

Claims (10)

A package substrate including a plurality of bonding pads; A plurality of semiconductor chips mounted on the upper surface of the above-mentioned package substrate, each comprising a plurality of pads, wherein the plurality of pads include a first data pad to an eighth data pad; and A plurality of wires connecting each of the above plurality of pads; comprising, The above plurality of semiconductor chips include a first semiconductor chip to a fourth semiconductor chip, and The first to fourth data pads included in the first semiconductor chip and the first to fourth data pads included in the second semiconductor chip are each connected to each other through first to fourth wires, and The first to fourth wires are semiconductor packages separated from the third semiconductor chip and the fourth semiconductor chip.
In paragraph 1, A semiconductor package having at least one pad disposed between each of the first to eighth data pads that provides a power supply voltage or a ground voltage.
In paragraph 1, A semiconductor package having a pair of pads arranged between the fourth data pad and the fifth data pad to provide a differential clock signal.
In paragraph 1, A semiconductor package in which the lower surface of the second semiconductor chip contacts the upper surface of the first semiconductor chip.
In paragraph 4, A semiconductor package in which the lower surface of the fourth semiconductor chip contacts the upper surface of the third semiconductor chip.
In paragraph 1, A semiconductor package in which at least one of the third semiconductor chip and the fourth semiconductor chip is disposed between the first semiconductor chip and the second semiconductor chip.
In paragraph 6, A semiconductor package in which at least one of the first semiconductor chip and the second semiconductor chip is disposed between the third semiconductor chip and the fourth semiconductor chip.
In paragraph 6, A semiconductor package in which the lower surface of the fourth semiconductor chip contacts the upper surface of the third semiconductor chip.
A package substrate including a plurality of bonding pads; A plurality of semiconductor chips mounted on the upper surface of the above-mentioned package substrate, each comprising a plurality of pads, wherein the plurality of pads each include a first data pad to an eighth data pad; and A plurality of wires connecting each of the above plurality of pads; comprising, The above plurality of semiconductor chips include a first semiconductor chip to a fourth semiconductor chip, and The first to fourth data pads included in the first semiconductor chip and the first to fourth data pads included in the second semiconductor chip are each connected to each other through first to fourth wires, and the first to fourth wires are separated from the third semiconductor chip and the fourth semiconductor chip. The fifth to eighth data pads included in the third semiconductor chip and the fifth to eighth data pads included in the fourth semiconductor chip are each connected to each other through fifth to eighth wires, and the fifth to eighth wires are separated from the first semiconductor chip and the second semiconductor chip. A semiconductor package in which the lengths of the first to fourth wires are different from the lengths of the fifth to eighth wires.
A package substrate including a plurality of bonding pads; A plurality of semiconductor chips mounted on the upper surface of the above-mentioned package substrate, each comprising a plurality of pads, wherein the plurality of pads each include a first data pad to an eighth data pad; and A plurality of wires connecting each of the plurality of pads; comprising, The above plurality of semiconductor chips include a first semiconductor chip to a fourth semiconductor chip, and The first to fourth data pads included in the first semiconductor chip and the first to fourth data pads included in the second semiconductor chip are each connected to each other through first to fourth wires, and the first to fourth wires are separated from the third semiconductor chip and the fourth semiconductor chip. A semiconductor package in which the plurality of semiconductor chips are provided with the same clock signal through at least one wire, and based on the clock signal, the first semiconductor chip and the second semiconductor chip transmit a first data signal through the first to fourth data pads, and simultaneously the third semiconductor chip and the fourth semiconductor chip transmit a second data signal through the fifth to eighth data pads.

Description

Semiconductor Package The present invention relates to a semiconductor package. A semiconductor package comprises a package substrate and at least one semiconductor chip mounted on the package substrate, and a plurality of pads included in the semiconductor chip may be electrically connected to a plurality of bonding pads included in the package substrate by wires. In a semiconductor package including a memory chip, a method of stacking two or more semiconductor chips on the package substrate has been proposed to increase the storage capacity of the semiconductor package. While such a structure can efficiently increase the storage capacity of the semiconductor package, the input/output capacitance of the pads connected to the wires may increase as the semiconductor chips are connected through each wire. Therefore, there may be limitations in inputting and outputting signals at high speeds. FIG. 1 is a simplified block diagram of a system according to one embodiment of the present invention. FIG. 2 is a simplified cross-sectional view of a semiconductor package according to one embodiment of the present invention. FIG. 3 is a simplified plan view of a semiconductor package according to one embodiment of the present invention. Figure 4 is a cross-sectional view showing the cross-section in the AA' direction of Figure 3. Figure 5 is a cross-sectional view showing the cross-section in the BB' direction of Figure 3. FIG. 6 is a simplified plan view of a semiconductor package according to one embodiment of the present invention. Figure 7 is a cross-sectional view showing the cross-section in the CC' direction of Figure 6. Figure 8 is a cross-sectional view showing the cross-section in the DD' direction of Figure 6. FIG. 9 is a simplified plan view of a semiconductor package according to one embodiment of the present invention. FIG. 10 is a cross-sectional view showing the cross-section in the EE' direction of FIG. 9. FIG. 11 is a cross-sectional view showing the cross-section in the FF` direction of FIG. 9. FIGS. 12 and FIGS. 13 are plan views simply illustrating a semiconductor package according to one embodiment of the present invention. FIG. 14 is a simplified block diagram of a memory device according to one embodiment of the present invention. Hereinafter, preferred embodiments of the present invention are described as follows with reference to the attached drawings. FIG. 1 is a simplified block diagram of a system according to one embodiment of the present invention. Referring to FIG. 1, a system according to one embodiment of the present invention may include a host (10) and a memory device (20) as a storage system that follows the UFS standard published by JEDEC (Joint Electron Device Engineering Council). However, the system according to one embodiment of the present invention is not necessarily limited to a storage system that follows the UFS standard, and the host (10) and the memory device (20) may exchange data in a manner different from the UFS standard. The host (10) may include a host controller (12), an application, a host driver, a host memory, and a UIC (UFS interconnect) layer (11). The host (10) can control the overall operation of the semiconductor device, specifically the operation of other components that make up the semiconductor device. The memory device (20) can function as a non-volatile storage device that stores data regardless of whether power is supplied, and can have a relatively large storage capacity. The memory device (20) may include a UIC layer (21), a memory controller (22), and a non-volatile memory (23), etc. Input signals and output signals can be transmitted and received through the UIC layer (11) of the host (10) and the UIC layer (21) of the memory device (20). Referring to FIG. 1, the memory controller (22) and the UIC layer (21) are shown separately, but are not limited thereto, and the UIC layer (21) may be included in the memory controller (22). Also, as previously described, if the communication method between the host (10) and the memory device (20) does not follow the UFS standard, the UIC layers (11, 21) may be replaced with other interfaces. The memory device (20) may include a memory controller (22) and a non-volatile memory (23) that stores data under the control of the memory controller (22). The non-volatile memory (23) may be composed of a plurality of memory units, and such memory units may include V-NAND (Vertical NAND) flash memory with a 2D structure or a 3D structure, but may also include other types of non-volatile memory such as PRAM and/or RRAM. The memory device (20) may be included in a semiconductor device while physically separated from the host (10), or it may be implemented within the same package as the host (10). Additionally, the memory device (20) may take the form of a solid state device (SSD) or a memory card. Such a memory device (20) may be a device to which standard protocols such as UFS, eMMC (embedded multi-media card), or NVMe (n