KR-20260067653-A - SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

KR20260067653AKR 20260067653 AKR20260067653 AKR 20260067653AKR-20260067653-A

Abstract

A semiconductor package according to an embodiment comprises: a first package including a first redistribution structure, a first molding member disposed on the first redistribution structure, a second redistribution structure disposed on the first molding member, and a first vertical connecting conductor that penetrates the first molding member along a vertical direction to electrically connect the first redistribution structure and the second redistribution structure to each other; a second package including a third redistribution structure, a second molding member disposed on the third redistribution structure, a fourth redistribution structure disposed on the second molding member, and a second vertical connecting conductor that penetrates the second molding member along a vertical direction to electrically connect the third redistribution structure and the fourth redistribution structure to each other; and a connecting bump disposed between the first package and the second package and electrically connecting the second redistribution structure and the third redistribution structure. and includes a package cover layer comprising a first portion disposed between the first package and the second package and surrounding the connection bump, and a second portion extending from the first portion and surrounding the side of the second package.

Inventors

신형진
권용태
박병진
김효영
류지혜

Assignees

주식회사 네패스

Dates

Publication Date: 20260513
Application Date: 20241106

Claims (15)

A first package comprising a first redistribution structure, a first molding member disposed on the first redistribution structure, a second redistribution structure disposed on the first molding member, and a first vertical connecting conductor that penetrates the first molding member along a vertical direction to electrically connect the first redistribution structure and the second redistribution structure to each other; A second package comprising a third redistribution structure, a second molding member disposed on the third redistribution structure, a fourth redistribution structure disposed on the second molding member, and a second vertical connecting conductor that penetrates the second molding member along a vertical direction to electrically connect the third redistribution structure and the fourth redistribution structure to each other; A connecting bump disposed between the first package and the second package and electrically connecting the second redistribution structure and the third redistribution structure; and, A semiconductor package comprising a package cover layer including a first portion disposed between the first package and the second package and surrounding the connection bump, and a second portion extending from the first portion and surrounding the side of the second package.
In paragraph 1, The first package further comprises a first semiconductor chip embedded within the first molding member and a second semiconductor chip disposed on the second redistribution structure. The second package further comprises a third semiconductor chip embedded within the second molding member and a fourth semiconductor chip disposed on the fourth redistribution structure. The second semiconductor chip is embedded in the first portion of the package cover layer, forming a semiconductor package.
In paragraph 2, The second package further includes a second molding member disposed on the fourth redistribution structure and molding the fourth semiconductor chip, and A semiconductor package, wherein the above package cover layer covers the side of the second molding member of the second package.
In paragraph 2, A semiconductor package, wherein the above package cover layer further comprises a third part extending from the second part and molding the fourth semiconductor chip.
In any one of paragraphs 1 through 4, The second portion of the package cover layer has a first horizontal width and a second horizontal width that are different from each other along the perimeter direction of the side of the second package, in a semiconductor package.
In any one of paragraphs 1 through 4, Each of the above package cover layer and the above second package includes a plurality of sides, and At least one of the plurality of sides of the second package is aligned along a vertical direction with at least one of the plurality of sides of the package cover layer, and A semiconductor package in which the above package cover layer does not contact at least one side of the aligned second package.
In paragraph 3, The upper surface of the package cover layer is positioned lower than the upper surface of the second package, and A semiconductor package in which at least a portion of the side of the second molding member does not contact the package cover layer.
In paragraph 3, The upper surface of the package cover layer is positioned lower than the upper surface of the second package, and A semiconductor package, wherein the second portion of the package cover layer covers the upper surface of the second molding member.
In any one of paragraphs 1 through 4, The first redistribution structure and the second redistribution structure have a symmetrical structure centered on the first molding member, The above third redistribution structure and the above fourth redistribution structure have a symmetrical structure centered on the above second molding member, and A semiconductor package in which the first and second redistribution structures of the first package have a symmetrical structure with respect to the third and fourth redistribution structures of the second package, centered on the first portion of the package cover layer.
In any one of paragraphs 1 through 3, It further includes a third package disposed on the second package above, and The above third package is a semiconductor package comprising a fifth redistribution structure, a fourth molding member disposed on the fifth redistribution structure, a sixth redistribution structure disposed on the fourth molding member, and a third vertical connecting conductor that penetrates the fourth molding member along a vertical direction to electrically connect the fifth redistribution structure and the sixth redistribution structure to each other.
In Paragraph 10, The outer width of the third package is smaller than the outer width of the first package and the outer width of the second package, and A semiconductor package, wherein the above package cover layer further comprises a fourth part extending from the third part toward the third package and arranged to surround the side of the third package.
In Paragraph 11, A semiconductor package comprising a package cover layer including a first package cover layer including the first part and the second part, and a second package cover layer disposed on the first package cover layer and including the third part and the fourth part.
A step of manufacturing a first package comprising: a first redistribution structure on a first carrier member; a first molding member disposed on the first redistribution structure; a first semiconductor chip embedded in the first molding member; a second redistribution structure disposed on the first molding member; and a first vertical connecting conductor penetrating the first molding member along a vertical direction to electrically connect the first redistribution structure and the second redistribution structure to each other. A step of manufacturing a second package comprising: a third redistribution structure on a second carrier member; a second molding member disposed on the third redistribution structure; a third semiconductor chip embedded within the second molding member; a fourth redistribution structure disposed on the second molding member; and a second vertical connecting conductor penetrating the second molding member along a vertical direction to electrically connect the third redistribution structure and the fourth redistribution structure to each other. A step of removing the second carrier member and placing a first connection bump on the lower part of the third redistribution structure of the second package; A step of coupling the second package onto the second redistribution structure of the first package using the first connection bump; and A method for manufacturing a semiconductor package, comprising the step of forming a package cover layer including a first portion filling the space between the first package and the second package, and a second portion extending from the first portion and surrounding the side of the second package.
In Paragraph 13, Before combining the second package, the method further includes the step of mounting a second semiconductor chip on the second rewiring structure of the first package. The second package is coupled to the first package through the first connection bump after the second semiconductor chip is mounted, and The method further includes the step of mounting a fourth semiconductor chip on the fourth redistribution structure of the second package after the first package and the second package are combined and before forming the package cover layer. The first portion of the package cover layer is provided to mold the second semiconductor chip, and A method for manufacturing a semiconductor package, wherein the above package cover layer further comprises a third part for molding the fourth semiconductor chip.
In Paragraph 14, After the step of placing the first connection bump, a third package comprising, on a third carrier member, a fifth redistribution structure, a third molding member disposed on the fifth redistribution structure, a fifth semiconductor chip embedded in the third molding member, a sixth redistribution structure disposed on the third molding member, and a third vertical connection conductor penetrating the third molding member along a vertical direction to electrically connect the fifth redistribution structure and the sixth redistribution structure to each other; and The method further includes the step of removing the third carrier member and placing a second connection bump on the lower part of the fifth redistribution structure of the third package. After the fourth semiconductor chip is mounted and before forming the package cover layer, a step of coupling the third package onto the fourth rewiring structure of the second package using the second connection bump; and The method further includes the step of mounting a sixth semiconductor chip on the sixth redistribution structure of the third package after the second package and the third package are combined and before forming the package cover layer. A method for manufacturing a semiconductor package, wherein the above package cover layer is formed by further including a fourth part extending from the third part and surrounding the side of the third package, and a fifth part disposed on the fourth part and molding the sixth semiconductor chip.

Description

Semiconductor Package and Method of Manufacturing the Same The embodiments relate to semiconductor packages, and in particular to highly integrated semiconductor packages and methods for manufacturing the same. Due to the increasing performance of various mobile devices, the number of input/output (I/O) terminals required in semiconductors is growing. Accordingly, Wafer Level Packaging (WLP) technology, which performs semiconductor packaging processes at the wafer level and separates the wafer-level semiconductor packages into individual units, is gaining attention. Fan-Out Wafer Level Package (FOWLP) or Fan-Out Panel Level Package (FOPLP) is a technology that mounts semiconductor chips directly onto a wafer rather than on a circuit board (e.g., a PCB). For semiconductor packages manufactured using FOWLP and/or FOPLP, manufacturing costs can be lowered by eliminating the need for a circuit board, and it enables package miniaturization, improved heat dissipation, reduced power consumption, and enhanced frequency bandwidth. FOWLP or FOPLP is manufactured by attaching individual dies to a carrier, molding them with a molding member, and subsequently performing processes such as forming a fan-out type redistribution layer (RDL) and bumping. The aforementioned semiconductor packages require multifunctionality, high performance, miniaturization, and lightweighting, and consequently, high integration is required. Accordingly, research is being conducted on Package-on-Package (PFP) type semiconductor packages, in which a semiconductor package with different functions is stacked on top of a single semiconductor package, in order to provide multifunctional semiconductor packages. However, conventional semiconductor packages have limitations in achieving high integration. Furthermore, in conventional semiconductor packages, stress may occur during the process of combining multiple packages, and electrical and/or mechanical reliability may be degraded by the aforementioned stress. For example, if stress is concentrated in the area where the terminals of semiconductor devices placed in each of the multiple packages are connected, the electrical and/or mechanical reliability of the semiconductor package may be degraded. Alternatively, if stress is concentrated in the area where multiple packages are connected to each other, electrical disconnection between the multiple packages may occur. Therefore, there is a need for technology that enables high integration while improving electrical and/or mechanical reliability. FIG. 1 is a cross-sectional view showing a semiconductor package according to a first embodiment. Figure 2 is a top view of the semiconductor package of Figure 1 as seen from the top direction. FIGS. 3a to 3l are cross-sectional views showing the manufacturing method of a semiconductor package according to the first embodiment shown in FIGS. 1 and 2 in process order. FIG. 4 is a cross-sectional view showing a semiconductor package according to a second embodiment. Figure 5 is a top view of the semiconductor package of Figure 4 as seen from the top direction. FIG. 6 is a cross-sectional view showing a semiconductor package according to a third embodiment. FIGS. 7 and 8 are plan views of various embodiments of the semiconductor package of FIG. 6 viewed from the upper direction. FIG. 9 is a cross-sectional view showing a semiconductor package according to a fourth embodiment. FIG. 10 is a cross-sectional view showing a semiconductor package according to the fifth embodiment. FIG. 11 is a cross-sectional view showing a semiconductor package according to the 6th embodiment. FIG. 12a is a cross-sectional view showing a semiconductor package according to the seventh embodiment. FIG. 12b is a cross-sectional view showing a semiconductor package according to the eighth embodiment. FIG. 13 is a cross-sectional view showing a semiconductor package according to the ninth embodiment. FIG. 14 is a cross-sectional view showing a semiconductor package according to the 10th embodiment. FIGS. 15a to 15j are cross-sectional views showing the manufacturing method of a semiconductor package illustrated in FIG. 14 in process order. The purpose, means, and resulting effects of the present invention will become clearer through the following detailed description in conjunction with the attached drawings, and accordingly, a person skilled in the art to which the present invention pertains will be able to easily implement the technical concept of the present invention. Furthermore, in describing the present invention, if it is determined that a detailed description of known technology related to the present invention may unnecessarily obscure the essence of the present invention, such detailed description will be omitted. The terms used in this specification are for describing embodiments and are not intended to limit the invention. In this specification, the singular form includes the plural form as appropriate unless specifically sta