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KR-20260067674-A - SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

KR20260067674AKR 20260067674 AKR20260067674 AKR 20260067674AKR-20260067674-A

Abstract

One embodiment of the present disclosure provides a semiconductor package comprising: upper pads disposed on the upper side, a first insulating layer having openings that expose the upper pads, and a second insulating layer disposed on the edge of the first insulating layer having an open portion that exposes the openings; a semiconductor chip stack mounted on the package substrate and comprising lower pads disposed on the lower side, wherein the semiconductor chip stack comprises a plurality of semiconductor chips stacked on the package substrate such that the front side faces the package substrate, each having a front side on which connection pads are disposed and a rear side opposite to the front side, the front side facing the package substrate, a mold layer covering the plurality of semiconductor chips, and connecting wires extending within the mold layer and electrically connecting the corresponding connection pads and the lower pads; and a semiconductor package comprising connecting bumps electrically connected to the package substrate and below the semiconductor chip stack.

Inventors

  • 이은수

Assignees

  • 삼성전자주식회사

Dates

Publication Date
20260513
Application Date
20241106

Claims (10)

  1. A package substrate comprising upper pads disposed on the upper portion, a first insulating layer having openings that expose the upper pads, and a second insulating layer disposed on the edge of the first insulating layer and having an open portion that exposes the openings; A semiconductor chip stack including lower pads disposed on the package substrate and mounted on the above package substrate, The above semiconductor chip stack is, A plurality of semiconductor chips stacked on a package substrate, each having a front surface on which connection pads are arranged and a rear surface opposite to the front surface, such that the front surface faces the package substrate. A mold layer covering the plurality of semiconductor chips, and It includes connecting wires that extend within the mold layer and electrically connect the corresponding connection pads and the lower pads; and A semiconductor package electrically connected to the above package substrate and comprising connection bumps below the semiconductor chip stack.
  2. In paragraph 1, A semiconductor package further comprising an adhesive layer between the second insulating layer and the semiconductor chip stack.
  3. In paragraph 2, A semiconductor package, wherein the adhesive layer surrounds the lower pads and the connection bumps on the first insulating layer.
  4. In paragraph 2, A semiconductor package having an adhesive layer that extends along a direction parallel to the upper surface of the first insulating layer on the first insulating layer and contacts the side of the second insulating layer, and has a portion that contacts at least a part of the upper surface of the second insulating layer and the side of the lower region of the semiconductor chip stack.
  5. In paragraph 1, Each of the above connection bumps is, A first portion in contact with the upper pads within the opening; and It includes a second part connected to the first part and positioned below the lower pads, The above second portion is a semiconductor package in contact with the upper surface of the above first insulating layer.
  6. In paragraph 5, A semiconductor package in which the horizontal width of the second part is greater than the horizontal width of the first part.
  7. In paragraph 1, A semiconductor package in which the lower surface of the mold layer of the semiconductor chip stack is at a level lower than the level of the upper surface of the second insulating layer.
  8. In paragraph 1, The semiconductor chip stack has an undercut region formed along the edge of the lower region of the mold layer, The semiconductor package further comprises an adhesive layer disposed between the package substrate and the semiconductor chip stack and filling at least a portion of the undercut area.
  9. Providing a package substrate comprising upper pads disposed on the upper portion, a first insulating layer having openings that expose the upper pads, and a second insulating layer having an open portion that exposes the openings at the edge of the first insulating layer; Providing semiconductor chip stacks, Providing the above semiconductor chip stack is, Stacking a plurality of semiconductor chips such that each has a front surface on which first connection pads are arranged and a rear surface opposite to the front surface, and the front surface is exposed toward a first direction. Forming connecting wires extending in the first direction on the first connection pads, Forming a mold layer covering the plurality of semiconductor chips and the connecting wires, and Includes forming second connection pads on the connection wires so as to face the first connection pads; Forming connection bumps on the second connection pads; and A method for manufacturing a semiconductor package, comprising mounting the semiconductor chip stack on the package substrate such that the connection bumps contact the upper pads within the openings.
  10. In Paragraph 9, It further includes forming an adhesive layer between the second insulating layer and the semiconductor chip stack, A method for manufacturing a semiconductor package, wherein the adhesive layer extends on the first insulating layer in a direction parallel to the upper surface of the first insulating layer, surrounds the second connection pads and the connection bumps, and contacts the upper surface of the second insulating layer and the side of the lower region of the semiconductor chip stack.

Description

Semiconductor Package and Method of Manufacturing the Same The present disclosure relates to a semiconductor package and a method for manufacturing the same. With the development of the electronics industry, there is an increasing demand for high functionality, high speed, and miniaturization of electronic components. In line with this trend, semiconductor packaging technology that embeds multiple semiconductor chips into a single package is being developed. FIG. 1a is a cross-sectional view illustrating a semiconductor package according to an exemplary embodiment. Figure 1b is a partial enlarged view illustrating area 'A' of Figure 1a. FIG. 2 is a partial enlarged view of a semiconductor package according to an exemplary modification example. FIG. 3a is a cross-sectional view illustrating a semiconductor package according to an exemplary embodiment. Figure 3b is a partial enlarged view illustrating area 'B' of Figure 3a. FIGS. 4 to 10 are cross-sectional views illustrated in the order of process to explain a method for manufacturing a semiconductor package according to an exemplary embodiment. FIG. 11 is a cross-sectional view illustrated in the process sequence to explain a method for manufacturing a semiconductor package according to an exemplary embodiment. In the following, terms such as 'top', 'upper part', 'upper surface', 'lower', 'lower part', 'lower surface', 'side surface', 'top', and 'bottom' are understood to refer to the drawings, except where otherwise indicated by drawing symbols. Terms such as "upper part", "middle", and "lower part" may be replaced by other terms, such as "first", "second", and "third", to describe the components of the specification. While terms such as "first", "second", and "third" may be used to describe various components, these components are not limited by these terms, and "first component" may be named "second component". Hereinafter, preferred embodiments of the present disclosure are described as follows with reference to the attached drawings. FIG. 1a is a cross-sectional view illustrating a semiconductor package according to an exemplary embodiment. Figure 1b is a partial enlarged view illustrating area 'A' of Figure 1a. Referring to FIG. 1a and FIG. 1b, a semiconductor package (100) of an exemplary embodiment may include a package substrate (300), a semiconductor chip stack (110) mounted on the package substrate (300), connection bumps (150), and an adhesive layer (200). A semiconductor chip stack (110) may include a plurality of semiconductor chips (120), a mold layer (130), and connecting wires (WR). In one embodiment, the semiconductor chip stack (110) may further include lower pads (140) disposed at the bottom. A plurality of semiconductor chips (120) may be semiconductor wafers on which integrated circuits (ICs) are formed. The semiconductor wafer may include, for example, semiconductor elements such as silicon and germanium, or semiconductor compounds such as SiC (silicon carbide), GaAs (gallium arsenide), InAs (indium arsenide), and InP (indium phosphide). The plurality of semiconductor chips (120) may be bare semiconductor chips without separate bumps or wiring layers formed thereon, but are not limited thereto, and may be packaged type semiconductor chips. A plurality of semiconductor chips (120) may include logic chips such as a central processor (CPU), a graphics processor (GPU), a field programmable gate array (FPGA), an application processor (AP), a digital signal processor, an encryption processor, a microprocessor, a microcontroller, an analog-to-digital converter, and an ASIC (application-specific IC), as well as memory chips including volatile memory such as DRAM (dynamic RAM) and SRAM (static RAM), and non-volatile memory such as PRAM (phase change RAM), MRAM (magnetic RAM), RRAM (resistive RAM), and flash memory. A plurality of semiconductor chips (120) may be arranged such that the connection pads (120P) face the package substrate (300). The plurality of semiconductor chips (120) may have a front surface on which the connection pads (120P) are arranged and a rear surface opposite to the front surface, and may be stacked such that the front surface faces the package substrate (300). The plurality of semiconductor chips (120) may be stacked in a shifted form such that each connection pad (120P) is exposed downward. An adhesive film layer (125) may be disposed on the rear surface of each of the plurality of semiconductor chips (120). The adhesive film layer (125) may include a die attach film (DAF). For example, a plurality of semiconductor chips (120) may include a first semiconductor chip (121), a second semiconductor chip (122), a third semiconductor chip (123), and a fourth semiconductor chip (124) stacked sequentially from top to bottom. The first semiconductor chip (121) may include first connection pads (121P), the second semiconductor chip (122) may include second connection pads (122P), the third semiconductor chip (123) may include t