KR-20260067730-A - SEMICONDUCTOR DEDVICE AND METHOD FOR FABRICATING THE SAME

Abstract

A semiconductor device according to one embodiment of the present invention may include a first gate extending in a first direction, an island gate adjacent to one end of the first gate with respect to the first direction, a second gate spaced apart from the first gate in a second direction perpendicular to the first direction and extending in the first direction, and a contact plug in contact with the island gate and the second gate.

Inventors

• 이연규
• 성민철
• 류승욱

Assignees

• 에스케이하이닉스 주식회사

Dates

Publication Date

20260513

Application Date

20241106

Claims (18)

1. A first gate extending in the first direction; An island gate adjacent to one end of the first gate with respect to the first direction; A second gate spaced apart from the first gate in a second direction perpendicular to the first direction and extending in the first direction; and A semiconductor device comprising a contact plug in contact with the island gate and the second gate.
2. In Article 1, The above-mentioned island gate has a square shape, and The second gate is a semiconductor device that surrounds at least three sides of the island gate.
3. In Article 2, The semiconductor device comprising a bridge portion located between the island gate and the first gate, wherein the second gate is the second gate.
4. In Article 1, The above second gate is a semiconductor device in contact with the above island gate.
5. In Article 1, A semiconductor device further comprising a bit line extending in the second direction, spaced apart from the first gate, with respect to a third direction perpendicular to the first direction and the second direction.
6. In Article 5, It further includes an active region in contact with the above bitline, and A semiconductor device comprising an active region that contacts the bit line, a horizontal portion extending in the second direction, and a vertical portion extending in the third direction.
7. In Article 6, The above vertical portion is a semiconductor device located between the first gate and the second gate.
8. In Article 7, The above first gate is a semiconductor device located between the vertical portions each comprising the adjacent active regions.
9. In Article 7, The above active region is a semiconductor device comprising an oxide semiconductor.
10. In Article 1, A semiconductor device further comprising a separation region separating adjacent second gates.
11. In Article 10, The above separation region is a semiconductor device located between the first gate and the island gate.
12. In Article 10, The above separation region is a semiconductor device that contacts one end of the second gate with respect to the first direction.
13. In Article 1, A semiconductor device in which the voltage provided to the first gate and the voltage provided to the second gate are different.
14. In Article 13, A semiconductor device in which the voltage provided to the first gate is the ground voltage.
15. In Article 1, Another island gate adjacent to the other end of the first gate with respect to the first direction; and A semiconductor device further comprising another contact plug electrically connected to the other island gate.
16. In Article 15, The above contact plug and the other contact plug are semiconductor devices located diagonally with respect to the center of the first gate.
17. A first gate extending in the first direction; A bit line extending in a second direction perpendicular to the first direction above; A second gate spaced apart from the first gate in the second direction; An active region comprising a horizontal portion in contact with the bitline and a vertical portion extending in a third direction perpendicular to the first direction and the second direction; An island gate adjacent to one end of the first gate with respect to the first direction; and It includes a contact plug that overlaps the above-mentioned island gate and the above-mentioned 2nd gate, and The above vertical portion is a semiconductor device located between the first gate and the second gate.
18. In Article 17, A semiconductor device further comprising a separation region separating adjacent second gates.

Description

Semiconductor Device and Method for Manufacturing the Same The present invention relates to a semiconductor device, and more specifically, to a semiconductor device having a memory cell. As miniaturization and increased integration density of semiconductor devices have emerged as major challenges, memory cells included in semiconductor devices can be formed to have a three-dimensional pattern, thereby improving the operating characteristics of the memory cells. FIG. 1 is a schematic perspective view of a semiconductor device according to one embodiment of the present disclosure. FIG. 2a is a cross-sectional view of a semiconductor device according to one embodiment of the present disclosure. FIG. 2b is a cross-sectional view of a semiconductor device according to another embodiment of the present disclosure. FIG. 2c is a cross-sectional view of a semiconductor device according to another embodiment of the present disclosure. FIG. 2d is a cross-sectional view of a semiconductor device cut along the X1-X1' cutting line of FIG. 2a. FIG. 2e is a cross-sectional view of a semiconductor device cut along the X2-X2' cutting line of FIG. 2b. FIG. 2f is a cross-sectional view of a semiconductor device cut along the X3-X3' cutting line of FIG. 2c. FIGS. 3a to 16a are perspective views for illustrating the manufacturing steps of a semiconductor device according to one embodiment of the present disclosure. FIGS. 3b to 16b are cross-sectional views in one direction for illustrating the manufacturing steps of a semiconductor device according to one embodiment of the present disclosure. FIGS. 3c to 15c are cross-sectional views in different directions intended to explain the manufacturing steps of a semiconductor device according to one embodiment of the present disclosure. FIG. 17 is a schematic perspective view of a semiconductor device according to another embodiment of the present disclosure. FIG. 18a is a cross-sectional view of a semiconductor device according to another embodiment of the present disclosure. FIG. 18b is a cross-sectional view of a semiconductor device according to another embodiment of the present disclosure. FIG. 18c is a cross-sectional view of a semiconductor device cut along the X4-X4' cutting line of FIG. 18a. FIG. 18d is a cross-sectional view of a semiconductor device cut along the X5-X5' cutting line of FIG. 18b. FIGS. 19a to 31a are perspective views illustrating the manufacturing steps of a semiconductor device according to another embodiment of the present disclosure. FIGS. 19b to 31b are cross-sectional views in one direction for illustrating the manufacturing steps of a semiconductor device according to another embodiment of the present disclosure. FIGS. 19c to 31c are cross-sectional views in different directions intended to illustrate the manufacturing steps of a semiconductor device according to another embodiment of the present disclosure. FIG. 32 is a cross-sectional perspective view of a semiconductor device according to another embodiment of the present disclosure. Hereinafter, various embodiments of the present disclosure are described with reference to the accompanying drawings. The advantages and features of the present disclosure and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, this is not intended to limit the present invention to specific embodiments. The present invention is not limited to the embodiments but can be implemented in various different forms and should be understood to include various modifications, equivalents, and/or alternatives to the embodiments of the present disclosure. In addition, it should be noted that when assigning reference numerals to the components of each drawing, the same components are to have the same numeral whenever possible, even if they are shown in different drawings. In describing the embodiments of the present disclosure, if it is determined that a detailed description of related known configurations or functions would hinder understanding of the embodiments of the present disclosure, such detailed description is omitted. In the specification, the singular form includes the plural form unless specifically stated otherwise in the text. As used in the specification, ‘comprises’ and/or ‘comprising’ do not exclude the presence or addition of one or more other components, steps, actions, and/or elements to the mentioned components, steps, actions, and/or elements. Hereinafter, a semiconductor device and a method for manufacturing the same according to embodiments of the present disclosure will be described with reference to the drawings. FIG. 1 is a schematic perspective view of a semiconductor device (1) according to one embodiment of the present disclosure. The structure of the semiconductor device (1) is explained with reference to FIG. 1. A semiconductor device (1) may include a substrate (LS) and a plurality of memory cells