Search

KR-20260067748-A - SEMICONDUCTOR CHIP AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME

KR20260067748AKR 20260067748 AKR20260067748 AKR 20260067748AKR-20260067748-A

Abstract

A semiconductor chip and a semiconductor package having reduced electrical resistance are provided. A semiconductor chip according to some embodiments comprises a device layer including a semiconductor element disposed on the front surface of a substrate and a first through-via extending in a first direction intersecting the front surface of the substrate and penetrating at least a portion of the substrate and the device layer, wherein the first through-via comprises a first front portion penetrating the front surface of the substrate and penetrating at least a portion of the device layer, and a first rear portion disposed within the substrate, connected to the first front portion, and disposed closer to the rear surface of the substrate than the first front portion, and the width of the first rear portion is greater than the width of the first front portion.

Inventors

  • 정현수

Assignees

  • 삼성전자주식회사

Dates

Publication Date
20260513
Application Date
20241106

Claims (10)

  1. A device layer comprising a semiconductor device disposed on the front surface of a substrate; and It includes a first through-via extending in a first direction intersecting the front surface of the substrate and penetrating at least a portion of the substrate and the device layer, The above-mentioned first penetrating via is, A first front portion penetrating the front surface of the substrate and penetrating at least a portion of the element layer, and It includes a first rear portion disposed within the substrate, connected to the first front portion, and disposed closer to the rear portion of the substrate than the first front portion. A semiconductor chip, wherein the width of the first rear portion is greater than the width of the first front portion.
  2. In Article 1, It further includes a first via insulating film surrounding the first through via, and The above-mentioned first via insulating film is, A first front insulating film surrounding the first front portion, and It includes a first rear insulating film surrounding the first rear portion, and A semiconductor chip in which the thickness of the first front insulating film is smaller than the thickness of the first rear insulating film.
  3. In Article 2, A semiconductor chip in which the dielectric constant of the first front insulating film is greater than the dielectric constant of the first rear insulating film.
  4. In Article 1, The above-mentioned first front part is, A first connecting part inserted into the first rear portion, and A semiconductor chip comprising a first extension portion that does not overlap with the first rear portion in a second direction intersecting the first direction.
  5. In Article 1, A semiconductor chip in which the width of the first front portion decreases as it approaches the first rear portion.
  6. A device layer comprising a semiconductor device disposed on the front surface of a substrate; A first through-via extending in a first direction intersecting the front surface of the substrate and penetrating at least a portion of the substrate and the element layer; and It includes a second through-via spaced apart from the first through-via in a second direction intersecting the first direction and penetrating at least a portion of the substrate and the device layer, The above-mentioned first penetrating via is, A first front portion penetrating the front surface of the substrate and penetrating at least a portion of the element layer, and It includes a first rear portion disposed within the substrate, connected to the first front portion, and disposed closer to the rear portion of the substrate than the first front portion. The above second penetrating via is, A second front portion penetrating the front surface of the substrate and penetrating at least a portion of the device layer, and It includes a second rear portion disposed within the substrate, connected to the second front portion, and disposed closer to the rear surface of the substrate than the second front portion, A semiconductor chip, wherein the width of the first rear portion is greater than the width of the second rear portion.
  7. In Article 6, The width of the first rear portion is larger than the width of the first front portion, and A semiconductor chip in which the width of the second rear portion is greater than the width of the second rear portion.
  8. In Article 6, The first front portion includes a first end portion disposed within the first rear portion, and The second front portion includes a second end portion disposed within the second rear portion, and A semiconductor chip in which the distance between the rear surface of the substrate and the first end according to the first direction and the distance between the rear surface of the substrate and the second end according to the first direction are different.
  9. In Article 6, A power signal is transmitted through the first through-via, and A semiconductor chip through which an input/output signal is transmitted via the second through-via.
  10. Package die; and It includes a plurality of semiconductor chips stacked in a first direction intersecting the above package die, and Each of the above plurality of semiconductor chips is, A device layer comprising a semiconductor device disposed on the front surface of a substrate, and A first through-via extending in the first direction and penetrating at least a portion of the substrate and the element layer, and It includes a second through-via spaced apart from the first through-via in a second direction intersecting the first direction and penetrating at least a portion of the substrate and the device layer, The above-mentioned first penetrating via is, A first front portion penetrating the front surface of the substrate and penetrating at least a portion of the element layer, and It includes a first rear portion disposed within the substrate, connected to the first front portion, and disposed closer to the rear portion of the substrate than the first front portion. The above second penetrating via is, A second front portion penetrating the front surface of the substrate and penetrating at least a portion of the device layer, and It includes a second rear portion disposed within the substrate, connected to the second front portion, and disposed closer to the rear surface of the substrate than the second front portion, The maximum width of the first rear portion is greater than the maximum width of the second rear portion, and The first through vias of the plurality of semiconductor chips overlap each other in the first direction, and A semiconductor package in which the second through-vias of the plurality of semiconductor chips overlap each other in the first direction.

Description

Semiconductor chip and semiconductor package including the same The present invention relates to a semiconductor chip and a semiconductor package including the same. Due to the development of the electronics industry, there is an increasing demand for high functionality, high speed, and miniaturization of electronic components. In response to this trend, methods can be utilized to mount multiple semiconductor chips by stacking them on a single package wiring structure, or to stack packages on top of each other. For example, package-in-package (PIP) or package-on-package (POP) semiconductor packages may be used. Meanwhile, TSVs (through silicon vias) that penetrate semiconductor chips are used, but due to the high integration of semiconductor chips, there are limitations in forming TSVs. FIG. 1 is a schematic diagram showing a semiconductor chip according to some embodiments. Figure 2 is an exemplary drawing showing an enlarged view of the R portion of Figure 1. FIG. 3 is an exemplary drawing showing an enlarged view of the R portion of FIG. 1 to illustrate a semiconductor chip according to several other embodiments. FIG. 4 is an exemplary drawing showing an enlarged view of the R portion of FIG. 1 to illustrate a semiconductor chip according to some other embodiments. FIG. 5 is an exemplary drawing showing an enlarged view of the R portion of FIG. 1 to explain a semiconductor chip according to some other embodiments. FIG. 6 is an exemplary drawing showing an enlarged view of the R portion of FIG. 1 to illustrate a semiconductor chip according to some other embodiments. FIG. 7 is an exemplary drawing showing an enlarged view of the R portion of FIG. 1 to illustrate a semiconductor chip according to some other embodiments. FIG. 8 is a schematic diagram showing a semiconductor package according to some embodiments. FIGS. 9 to 16 are schematic diagrams illustrating intermediate steps to explain a method for manufacturing a semiconductor chip according to some embodiments shown in FIG. 1. Prior to the detailed description of the embodiments, terms and words used in this specification and claims should not be interpreted as being limited to their ordinary or dictionary meanings, but should be interpreted in a meaning and concept consistent with the technical spirit of this disclosure, based on the principle that the inventor may appropriately define the concept of the terms to best describe his invention. Accordingly, the embodiments described in this specification and the configurations illustrated in the drawings are merely the most preferred embodiments of this disclosure and do not represent all of the technical spirit of this disclosure; therefore, it should be understood that various equivalents and modifications that can replace them may exist at the time of filing this application. In the following description, singular expressions include plural expressions unless the context clearly indicates otherwise. Terms such as "comprising" or "constituting" are intended to specify the existence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof. In this specification, singular expressions include plural expressions unless the context clearly indicates otherwise. Additionally, terms such as "first," "second," etc., may be used to describe various components, but said components are not limited by said terms, and said terms may be used for the purpose of distinguishing one component from another. Within the scope of the technical spirit of the present invention, the first component may be named the second component, and similarly, the second component may be named the first component. Furthermore, in the drawings, the shapes and sizes of the components may be exaggerated to emphasize clear explanations. Furthermore, it should be noted in advance that expressions such as upper side, top, lower side, bottom, side, front, and rear in the following description are based on the direction depicted in the drawings, and may be expressed differently if the direction of the object changes. The shapes and sizes of elements in the drawings may be exaggerated for clearer explanation. Hereinafter, embodiments according to the technical concept of the present invention will be described with reference to the attached drawings. FIG. 1 is a schematic diagram showing a semiconductor chip according to some embodiments. FIG. 2 is an exemplary diagram showing an enlarged view of the R portion of FIG. 1. Referring to FIGS. 1 and 2, a semiconductor chip (10) according to some embodiments may include a substrate (100), a device layer (110), a first through-via (200), and a second through-via (300). According to some embodiments, the semiconductor chip (10) may be an integrated circuit (IC) in which hundreds t