KR-20260067757-A - SEMICONDUCTOR PACKAGE

KR20260067757AKR 20260067757 AKR20260067757 AKR 20260067757AKR-20260067757-A

Abstract

It may include a semiconductor substrate, a device layer on the semiconductor substrate, a wiring layer on the device layer, and a buffer layer provided between the semiconductor substrate and the device layer or between the device layer and the wiring layer. The buffer layer may include a first buffer layer having a plurality of first holes spaced apart from each other, and a second buffer layer provided on the first buffer layer, wherein the second buffer layer includes a plurality of second holes spaced apart from each other, and each of the first holes of the buffer layer may be disposed between any two adjacent second holes.

Inventors

최재혁

Assignees

삼성전자주식회사

Dates

Publication Date: 20260513
Application Date: 20241106

Claims (10)

semiconductor substrate; A device layer on the semiconductor substrate above; A wiring layer on the above-mentioned device layer; and A buffer layer provided between the semiconductor substrate and the device layer or between the device layer and the wiring layer, wherein The above buffer layer is: A first buffer layer comprising a plurality of first holes spaced apart from each other; and It includes a second buffer layer provided on the first buffer layer, and The second buffer layer includes a plurality of second holes spaced apart from each other, and Each of the first holes of the above buffer layer is disposed between any two adjacent second holes among the above second holes in a semiconductor package.
In Article 1, The width of each of the first holes and the second holes is 3 μm to 10 μm, and The spacing between two adjacent second holes among the above second holes is uniform, and The gap between two adjacent first holes among the above first holes is uniform in the semiconductor package.
In Article 1, The above buffer layer is a semiconductor package interposed between the semiconductor substrate and the device layer.
semiconductor substrate; A device layer on the semiconductor substrate above; A wiring layer on the above-mentioned device layer; and A first buffer layer provided between the semiconductor substrate and the device layer or between the device layer and the wiring layer, wherein The first buffer layer includes first holes and second holes spaced apart from each other, and Each of the above first holes is recessed from the upper surface of the first buffer layer toward the interior of the first buffer layer, and Each of the above second holes is recessed from the lower surface of the first buffer layer toward the interior of the first buffer layer, and Each of the first holes of the first buffer layer is disposed between any two adjacent second holes among the second holes in a semiconductor package.
In Article 4, The first buffer layer above is a semiconductor package comprising an insulating polymer.
In Article 4, The level of the bottom surface of the first holes is higher than the level of the bottom surface of the second holes, and The distance from the level of the bottom surface of the first holes to the level of the bottom surface of the second holes is 1 μm to 2 μm for a semiconductor package.
In Article 4, A semiconductor package in which the width of each of the first holes and the second holes is 3 μm to 10 μm.
In Article 4, The above-mentioned device layer includes at least one passive device, and The wiring layer includes a connection pad protruding onto the upper surface of the wiring layer, and The first buffer layer is interposed between the device layer and the wiring layer, and The above passive element is electrically connected to the connection pad through a through-via penetrating the first buffer layer, and In a planar view, the first holes and the second holes of the first buffer layer are horizontally spaced apart from the through-via in a semiconductor package.
Package substrate; A semiconductor chip disposed on the above-mentioned package substrate; and A molding film surrounding the semiconductor chip on the above-mentioned package substrate, comprising: The above semiconductor chip is: semiconductor substrate; A wiring layer on the semiconductor substrate; and It includes a buffer layer interposed between the semiconductor substrate and the wiring layer, and The above buffer layer is: A first buffer layer comprising a plurality of first holes spaced apart from each other; and It includes a second buffer layer provided on the first buffer layer, and The second buffer layer includes a plurality of second holes spaced apart from each other, and From a planar perspective, the buffer layer has a grid structure in which the first holes and the second holes are spaced apart at regular intervals and alternately arranged, A semiconductor package in which the elastic modulus of the above buffer layer is smaller than the elastic modulus of the above semiconductor substrate.
In Article 9, The semiconductor chip further includes a device layer provided between the semiconductor substrate and the wiring layer, wherein The above device layer further includes at least one capacitor element provided within the device layer, and The above capacitor element is: First electrode; A capacitor dielectric film covering the first electrode with a uniform thickness; and It includes a second electrode covering the first electrode on the dielectric film of the capacitor, The above buffer layer is a semiconductor package interposed between the semiconductor substrate and the device layer.

Description

Semiconductor Package The present invention relates to a semiconductor package. With the development of the electronics industry, there is an increasing demand for high functionality, high speed, and miniaturization of electronic components. For example, there is a growing demand for high reliability, high speed, and/or multifunctionality for semiconductor devices within semiconductor packages. To meet these requirements, structures within semiconductor packages are becoming increasingly complex and highly integrated. As the high integration of structures within semiconductor packages intensifies, the reliability and mechanical stability of the semiconductor package may deteriorate. Therefore, much research is being conducted to improve the reliability and stability of semiconductor packages. FIG. 1 is a cross-sectional view illustrating a semiconductor package according to embodiments of the present invention. FIG. 2 is an enlarged view for explaining a part of a semiconductor package according to embodiments of the present invention, and is an enlarged view of part N of FIG. 1. FIG. 3 is an exploded perspective view illustrating a buffer layer of a semiconductor package according to embodiments of the present invention. FIG. 4 is a plan view illustrating a first buffer layer of a semiconductor package according to embodiments of the present invention. FIG. 5 is a plan view illustrating a second buffer layer of a semiconductor package according to embodiments of the present invention. FIG. 6 is a perspective view illustrating a part of a semiconductor package according to embodiments of the present invention. FIGS. 7 and FIGS. 8 are cross-sectional views illustrating a semiconductor package according to embodiments of the present invention. FIG. 9 is an enlarged view for explaining a part of a semiconductor package according to embodiments of the present invention, which is an enlarged view of part M of FIG. 8. FIG. 10 is an enlarged view for explaining a part of a semiconductor package according to embodiments of the present invention, which is an enlarged view of part O of FIG. 9. FIG. 11 is an enlarged view for illustrating a part of a semiconductor package according to embodiments of the present invention, which is an enlarged view of part M of FIG. 8. FIG. 12 is a flowchart for explaining a method for manufacturing a semiconductor package according to embodiments of the present invention. Figure 13 is a schematic diagram illustrating the first step of Figure 12. Figure 14 is a schematic diagram illustrating the second step of Figure 12. Figure 15 is a schematic diagram illustrating the third step of Figure 12. Hereinafter, a semiconductor package according to the concept of the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view for illustrating a semiconductor package according to embodiments of the present invention. FIG. 2 is an enlarged view for illustrating a part of a semiconductor package according to embodiments of the present invention, which is an enlarged view of portion N of FIG. 1. With reference to FIG. 1 and FIG. 2, a first semiconductor chip (100) may be provided, wherein a first direction (D1) and a second direction (D2) may be parallel to the upper surface of the first semiconductor chip (100). The first direction (D1) and the second direction (D2) may be perpendicular to each other. A third direction (D3) may be perpendicular to the upper surface of the first semiconductor chip (100). The first semiconductor chip (100) may include a first semiconductor substrate (110). The first semiconductor substrate (110) may include a semiconductor material. For example, the first semiconductor substrate (110) may include silicon (Si). Although not illustrated, integrated elements or integrated circuits may be provided on the lower surface of the first semiconductor substrate (110). For example, the integrated circuits may include memory circuits or logic circuits. A first interlayer insulating film (112) may be provided on the lower surface of the first semiconductor substrate (110). The first interlayer insulating film (112) may cover the lower surface of the first semiconductor substrate (110). The first interlayer insulating film (112) may cover the integrated element or integrated circuit. Internal wiring connected to the integrated element or integrated circuit may be exposed on the lower surface of the first interlayer insulating film (112). The first interlayer insulating film (112) may comprise a multilayer film comprising at least one of silicon oxide, silicon nitride, and silicon oxynitride. However, the present invention is not limited thereto. A buffer layer (MBL) may be provided on the lower surface of the first interlayer insulating film (112). The buffer layer (MBL) may cover the lower surface of the first interlayer insulating film (112). The buffer layer (MBL) may have at least one layer. The thickness of the buffer layer (MBL) i