KR-20260067764-A - BIAS CURRENT GENERATION CIRCUIT COMPRISING SELF-CORRECTING CIRCUIT, APPARATUS COMPRISING SPIKE NEURAL NETWORK DRIVEN BASED THEREON, AND METHOD FOR CORRECTING BIAS CURRENT

Abstract

An apparatus according to one embodiment of the present disclosure comprises a bias current generating circuit for generating a bias current, a synapse circuit including a weight register that performs a charge operation based on an input spike signal, a bias current, and a weight stored in the weight register, a membrane capacitor having a potential determined based on the charge operation of the synapse circuit, and a neuron circuit that generates an output spike signal based on a comparison between the potential of the membrane capacitor and a threshold potential, wherein the bias current generating circuit includes a self-correction circuit, the self-correction circuit includes a target input spike register, and the self-correction circuit can correct the bias current generated by the bias current generating circuit based on a value regarding the number of target input spikes stored in the target input spike register.

Inventors

• 오광일
• 김혁
• 이재진

Assignees

• 한국전자통신연구원

Dates

Publication Date

20260513

Application Date

20241106

Claims (20)

1. In a device comprising a spike neural network circuit that generates an output spike signal based on an input spike signal received from an axon line, Bias current generating circuit that generates bias current; A synapse circuit including a weight register, which performs a charge operation based on the input spike signal, the bias current, and the weight stored in the weight register; A membrane capacitor having a potential determined based on the charge operation of the above synaptic circuit; and A neuron circuit that generates a first output spike signal based on a comparison between the potential of the membrane capacitor and a threshold potential, wherein The above bias current generation circuit includes a self-correction circuit, and The above self-correction circuit includes a target input spike register, and A device characterized in that the self-correction circuit is configured to correct the bias current generated by the bias current generation circuit based on a value regarding the number of target input spikes stored in the target input spike register.
2. In Article 1, The above neuron circuit is characterized by generating the first output spike signal based on a comparison result that the potential of the membrane capacitor is lower than the threshold potential.
3. In Article 1, The above self-correction circuit is characterized by outputting a binary code for correcting the bias current.
4. In Article 1, The above self-correction circuit is: A replica synapse circuit configured to receive the input spike signal from the axon line and perform charge operations; A replica membrane capacitor having a potential determined based on the charge calculation of the above replica synapse circuit; A replica neuron circuit that generates a second output spike signal based on the potential of the above replica membrane capacitor; An input spike counter that receives the input spike signal from the exon line and receives the second output spike signal from the replica neuron circuit, and counts the number of spikes of the input spike signal until the second output spike signal is generated; A target input spike register that stores a value regarding the number of target input spikes; A comparator that compares the number of spikes counted above with the number of target input spikes; and A device characterized by including a binary code bit controller that modifies the binary code based on a comparison result.
5. In Article 4, The above binary code bit controller is, A device characterized by modifying the binary code by increasing the least significant bit within the upper bits of the binary code by 1 bit, based on a comparison result that the number of spikes counted above is less than the number of target input spikes.
6. In Article 5, The above binary code bit controller is, A device characterized by modifying the binary code by decreasing the least significant bit within the lower bits of the binary code by 1 bit based on a comparison result that the number of spikes counted above is greater than the number of target input spikes.
7. In Article 4, The above binary code bit controller stores a predetermined initial binary code, and The above replica neuron circuit generates the second output spike signal based on the first bias current according to the initial binary code, and The above input spike counter counts the number of spikes of the input spike signal until the second output spike signal is generated, and The above comparator compares the number of spikes with the number of target input spikes, and A device characterized by modifying the initial binary code into a first binary code by increasing the least significant bit within the upper bits of the initial binary code by 1, based on a comparison result that the number of spikes is less than the number of target input spikes.
8. In Article 4, The device is characterized in that the input spike counter resets the count value when the second output spike signal is generated by the replica neuron circuit.
9. In Article 4, The device is characterized in that the self-correction circuit terminates the correction procedure of the bias current based on the comparison result of the comparator that the number of spikes of the input spike signal counted by the input spike counter is equal to the number of target input spikes.
10. In Article 1, The above bias current generation circuit includes a current correction path connected to the self-correction circuit, and a synapse bias path through which a bias current flows that is provided to the spike neural network, wherein The above current correction path and the above synapse bias path are composed of the same current mirror including transistors, and A device characterized in that the magnitude of the current flowing in the current correction path is the same as the magnitude of the current flowing in the synapse bias path.
11. A bias current generation circuit that provides a bias current to a spike neural network circuit that generates an output spike signal based on an input spike signal from an axon line and corrects the bias current, A first group of transistors constituting a synapse bias path for providing the bias current to the spike neural network circuit; A second group of transistors configured with the same current mirror as the first group of transistors to form a current correction path; A third group of transistors including transistors for controlling the above bias current; and It includes a self-correction circuit that provides control signals according to a binary code for correcting the above bias current to the transistors of the third group, The above self-correction circuit is: A replica synapse circuit configured to receive the input spike signal from the axon line and perform charge operations; A replica membrane capacitor having a potential determined based on the charge calculation of the above replica synapse circuit; A replica neuron circuit that generates an output spike signal based on the potential of the above replica membrane capacitor; An input spike counter that receives the input spike signal from the exon line and receives the output spike signal from the replica neuron circuit, and counts the number of spikes of the input spike signal until the output spike signal is generated; A target input spike register that stores a value regarding the number of target input spikes; A comparator that compares the number of spikes counted above with the number of target input spikes; and A bias current generating circuit including a binary code bit controller that modifies the binary code based on a comparison result.
12. In Article 11, The above binary code bit controller is, A bias current generating circuit characterized by modifying the binary code by increasing the least significant bit within the upper bits of the binary code by 1 bit, based on a comparison result that the number of spikes counted above is less than the number of target input spikes.
13. In Article 12, The above binary code bit controller is, A bias current generating circuit characterized by modifying the binary code by decreasing the least significant bit within the lower bits of the binary code by 1 bit, based on a comparison result that the number of spikes counted above is greater than the number of target input spikes.
14. In Article 11, The above binary code bit controller stores a predetermined initial binary code, and The above replica neuron circuit generates the output spike signal based on a first bias current according to the initial binary code, and The above input spike counter counts the number of spikes of the input spike signal until the output spike signal is generated, and The above comparator compares the number of spikes with the number of target input spikes, and A bias current generating circuit characterized by modifying the initial binary code into the first binary code by increasing the least significant bit among the upper bits of the initial binary code by 1, based on a comparison result that the number of the first spikes is less than the number of target input spikes.
15. In Article 11, The above input spike counter is a bias current generating circuit characterized by resetting the count value when the output spike signal is generated by the above replica neuron circuit.
16. In Article 11, A bias current generation circuit characterized in that the self-correction circuit terminates the correction procedure of the bias current based on the comparison result of the comparator that the number of spikes of the input spike signal counted by the input spike counter is equal to the number of target input spikes.
17. A method for correcting a bias current provided to a spike neural network circuit that generates an output spike signal based on an input spike signal from an axon line, A step of receiving an input spike signal from the axon line by means of a replica synapse circuit and an input spike counter; A step of receiving an output spike signal generated by a replica neuron circuit based on the input spike signal and a bias current according to the binary code, by means of the input spike counter; A step of counting the number of spikes of the input spike signal until the output spike signal is generated by the input spike counter; A step of comparing the counted number of spikes with the target input spike count by means of a comparator; and A method comprising the step of modifying the binary code based on the comparison result by a binary code bit controller.
18. In Article 17, The step of modifying the binary code based on the above comparison result is, A method comprising the step of modifying the binary code by increasing the least significant bit within the upper bits of the binary code by 1 bit, based on a comparison result that the number of spikes counted above is less than the number of target input spikes.
19. In Article 17, The step of modifying the binary code based on the above comparison result is, A method comprising the step of modifying the binary code by decreasing the least significant bit within the lower bits of the binary code by 1 bit, based on a comparison result that the number of spikes counted above is greater than the number of target input spikes.
20. In Article 17, The above method is: A step of starting with a predetermined initial binary code, and generating the output spike signal based on a first bias current according to the initial binary code by the replica neuron circuit; A step of counting the number of spikes of the input spike signal until the output spike signal is generated by the input spike counter; and A step of comparing the number of spikes with the number of target input spikes by means of the comparator above; and A method comprising the step of modifying the initial binary code into a first binary code by increasing the least significant bit within the upper bits of the initial binary code by 1 bit, based on a comparison result that the number of spikes is less than the number of target input spikes.

Description

Bias current generation circuit comprising a self-correcting circuit, apparatus comprising a spike neural network driven based thereon, and method for correcting bias current The present disclosure relates to a spike neural network circuit, and more specifically, to a bias current generating circuit including a self-correcting circuit, an apparatus including a spike neural network driven based thereon, and a method for correcting the bias current. Artificial neural networks (ANNs) can process data or information in a manner similar to biological neural networks. Unlike perceptron-based or convolution-based neural networks, spike neural networks do not transmit signals of a specific level; instead, spike signals containing pulses that toggle for a short period of time can be transmitted. Spike neural network circuits can be implemented using semiconductor devices. Spike neural network circuits implemented as semiconductors are affected by the surrounding environment (e.g., temperature, humidity, changes in power supply voltage, etc.), which can cause errors in the computational results of the spike neural network. Therefore, there is a need for a self-correcting spike neural network circuit that possesses a function to compensate for changes in the surrounding environment after the spike neural network circuit is fabricated. FIG. 1 is a schematic diagram of a device according to one embodiment of the present document. FIG. 2 is a schematic diagram of a synapse circuit according to one embodiment of the present document. Figure 3 is a timing diagram to explain the operation of synaptic circuits and neuron circuits according to input spike signals applied through the axon lines. FIG. 4 is a schematic diagram of the I-DAC of FIG. 2 according to one embodiment of the present document. FIG. 5 is a schematic diagram of the bias current generating circuit of FIG. 1 according to one embodiment of the present document. FIG. 6 is a schematic diagram of the self-correction circuit of FIG. 5 according to one embodiment of the present document. FIG. 7 is a schematic diagram of a replica synapse circuit of FIG. 6 according to one embodiment of the present document. FIG. 8 is a table exemplarily showing binary code (B_code<7:0>) according to one embodiment of the present document. FIG. 9 is a timing diagram of an operation waveform to explain the operation of the self-correction circuit of FIG. 5 and FIG. 6 according to one embodiment of the present document. FIG. 10 is a flowchart illustrating an exemplary method for correcting bias current according to one embodiment of the present document. In the following, embodiments of the present disclosure will be described clearly and in detail so that a person skilled in the art can easily practice the present disclosure. Terms such as "unit" and "module" used below, or functional blocks illustrated in the drawings, may be implemented in the form of software configurations, hardware configurations, or combinations thereof. In order to clearly explain the technical concept of the present invention, detailed descriptions of redundant components are omitted below. In this document, each of the phrases such as "A or B", "at least one of A and B", "at least one of A or B", "A, B or C", "at least one of A, B and C", and "at least one of A, B, or C" may include any one of the items listed together with the corresponding phrase, or all possible combinations thereof. FIG. 1 is a schematic diagram of a device according to one embodiment of the present document. The device (1000) of FIG. 1 may be a device comprising a spike neural network circuit (1100) that generates an output spike signal based on an input spike signal (exon input pulse) received from exon lines (AXL1 to AXLn). The device (1000) may further comprise membrane capacitors (Cm1 to Cmn), neuron circuits (NC1 to NCn), and a bias current generating circuit (1200). The device (1000) may also comprise axon lines (AXL1 to AXLn) and membrane lines (MBL1 to MBLn). In the present document, an axon may be referred to as an axon, and a membrane may be referred to as a membrane. In the present document, an axon line and a membrane line may be simply replaced with an axon and a membrane, respectively. The bias current generating circuit (1200) can generate a bias current. For a node (gate) on a synapse circuit (SY11~SYnn) to which the bias current generating circuit (1200) is connected, a bias voltage can be determined by the bias current generating circuit (1200). A more detailed schematic diagram of the synapse bias current generating circuit (1200) according to one embodiment is shown in FIG. 5. The spike neural network circuit (1100) may include synapse circuits (SY11 to SYnn). The synapse circuits (SY11 to SYnn) can perform charge operations based on an input spike signal, a bias current, and weights stored in a weight register. In this document, the synapse circuit may be simply replaced with a synapse. A more detailed schematic di