KR-20260067810-A - SEMICONDUCOTR DEVICE

KR20260067810AKR 20260067810 AKR20260067810 AKR 20260067810AKR-20260067810-A

Abstract

A semiconductor device is provided. The semiconductor device comprises: a package substrate; a plurality of semiconductor chips stacked on the package substrate, each having a first sidewall; and a first conductive film electrically connected to the package substrate and extending over the first sidewalls of the plurality of semiconductor chips, wherein each of the plurality of semiconductor chips may include: a peripheral circuit structure comprising first bonding pads on a first surface of the substrate; a first cell array structure comprising a first stacked structure and second bonding pads bonded to the first bonding pads; and a first input/output pad disposed on the first sidewall and electrically connected to the first conductive film.

Inventors

이은혜
이근영
이인재

Assignees

삼성전자주식회사

Dates

Publication Date: 20260513
Application Date: 20241106

Claims (10)

Package substrate; A plurality of semiconductor chips stacked on the above-mentioned package substrate, each having a first sidewall; and A first conductive film that is electrically connected to the package substrate and extends over the first sidewalls of the plurality of semiconductor chips, wherein Each of the above plurality of semiconductor chips is: Peripheral circuit structure including first bonding pads on a first surface of a substrate; A first cell array structure comprising a first stacked structure and second bonding pads bonded to the first bonding pads; and A semiconductor device comprising a first input/output pad disposed on the first side wall and electrically connected to the first conductive film.
In paragraph 1, Each of the above plurality of semiconductor chips is: Further including a conductive contact between the first and second bonding pads and the first input/output pad, The first input/output pad is a semiconductor device electrically connected to the conductive contact and the first and second bonding pads.
In paragraph 2, The above-mentioned conductive contact is a semiconductor device in contact with the sidewalls of the first and second bonding pads.
In paragraph 1, The above peripheral circuit structure includes a peripheral interlayer insulating film surrounding the first bonding pads, and The first cell array structure comprises an interlayer insulating film surrounding the second bonding pads, wherein The first input/output pad is a semiconductor device disposed on the peripheral interlayer insulating film and the sidewalls of the interlayer insulating film.
In paragraph 1, A semiconductor device in which the first sidewalls of the plurality of semiconductor chips are aligned with each other.
In paragraph 1, A semiconductor device comprising a plurality of semiconductor chips each further including second input/output pads disposed on a second sidewall.
In paragraph 6, The first sidewall is a semiconductor device facing the second sidewall.
In paragraph 1, Each of the above plurality of semiconductor chips is: Vertical structures penetrating the first laminated structure; and A semiconductor device further comprising bit lines connected to the vertical structures, disposed between the second bonding pads and the first stacked structure in a vertical perspective.
Package substrate; A plurality of semiconductor chips stacked on the above-mentioned package substrate, each having a first sidewall; A molding film surrounding the plurality of semiconductor chips on the package substrate; and A first conductive film that is electrically connected to the package substrate and extends over the first sidewalls of the plurality of semiconductor chips, wherein Each of the above plurality of semiconductor chips is: A peripheral circuit structure comprising first bonding pads on a first surface of a substrate and second bonding pads on a second surface facing the first surface; A first cell array structure comprising third bonding pads bonded to the first bonding pads; and It includes a first input/output pad disposed on the first side wall and electrically connected to the first conductive film, and The above first cell array structure is: A first stacked structure comprising first insulating patterns and first gate patterns that are vertically alternately stacked; Vertical structures penetrating the first laminated structure; and A semiconductor device comprising bit lines electrically connected to the above vertical structures.
A peripheral circuit structure comprising first bonding pads on a first surface of a substrate and second bonding pads on a second surface of the substrate; and A first cell array structure facing the first surface above; A second cell array structure facing the second surface above; A first input/output pad on the first sidewall of the above peripheral circuit structure; and It includes a second input/output pad on the second sidewall of the above peripheral circuit structure, The above first cell array structure is: A first stacked structure comprising first insulating patterns and first gate patterns that are vertically alternately stacked; First vertical structures penetrating the first laminated structure; and It includes third bonding pads bonded to the first bonding pads, and The above second cell array structure is: A second stacked structure comprising second insulating patterns and second gate patterns that are vertically alternately stacked; Second vertical structures penetrating the second laminated structure; and A semiconductor device comprising fourth bonding pads bonded to the second bonding pads.

Description

Semiconductor Device The present invention relates to a semiconductor device and a semiconductor package including the same. In electronic systems requiring data storage, there is a demand for semiconductor devices capable of storing high-capacity data. Accordingly, methods to increase the data storage capacity of semiconductor devices are being studied. For example, as one method to increase the data storage capacity of semiconductor devices, a semiconductor device including memory cells arranged in three dimensions instead of memory cells arranged in two dimensions is being proposed. Furthermore, semiconductor packaging technology is required to integrate semiconductor devices, including memory cells, into a single package. In particular, semiconductor packages in which multiple components are integrated are required to achieve not only miniaturization but also excellent heat dissipation and electrical characteristics. FIG. 1 is a schematic diagram showing an electronic system including a semiconductor device according to an exemplary embodiment of the present invention. FIG. 2a is a plan view of a semiconductor device according to an exemplary embodiment of the present invention. FIG. 2b is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the present invention, showing a cross-section cut along the line A-A' of FIG. 2a. FIG. 3a is a plan view of a semiconductor device according to an exemplary embodiment of the present invention. FIG. 3b is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the present invention, showing a cross-section cut along the line B-B' of FIG. 3a. FIG. 4 is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the present invention. Figure 5 is an enlarged view showing part A of Figure 4. Figure 6 is an enlarged view showing part P1 of Figure 5. Figure 7 is an enlarged view showing part P2 of Figure 5. FIG. 8 is a cross-sectional view of a semiconductor package according to an exemplary embodiment of the present invention. FIG. 9 is a cross-sectional view of a semiconductor package according to an exemplary embodiment of the present invention. FIGS. 10 to 16 are drawings for explaining a method of manufacturing a semiconductor device according to an exemplary embodiment of the present invention. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a schematic diagram showing an electronic system including a semiconductor device according to an exemplary embodiment of the present invention. Referring to FIG. 1, an electronic system (1000) according to an exemplary embodiment of the present invention may include a semiconductor device (1100) and a controller (1200) electrically connected to the semiconductor device (1100). The electronic system (1000) may be a storage device or an electronic device including a storage device, comprising one or more semiconductor devices (1100). For example, the electronic system (1000) may be a solid state drive device (SSD), a Universal Serial Bus (USB), a computing system, a medical device, or a communication device, comprising one or more semiconductor devices (1100). The semiconductor device (1100) may be a non-volatile memory device, for example, a NAND flash memory device. The semiconductor device (1100) may include a first structure (1100F) and a second structure (1100S) on the first structure (1100F). In exemplary embodiments, the first structure (1100F) may be placed next to the second structure (1100S). The first structure (1100F) may be a peripheral circuit structure including a decoder circuit (1110), a page buffer (1120), and a logic circuit (1130). The second structure (1100S) may be a memory cell structure including a bit line (BL), a common source line (CSL), word lines (WL), first and second gate upper lines (UL1, UL2), first and second gate lower lines (LL1, LL2), and memory cell strings (CSTR) between the bit line (BL) and the common source line (CSL). In the second structure (1100S), each memory cell string (CSTR) may include lower transistors (LT1, LT2) adjacent to a common source line (CSL), upper transistors (UT1, UT2) adjacent to a bit line (BL), and a plurality of memory cell transistors (MCT) disposed between the lower transistors (LT1, LT2) and the upper transistors (UT1, UT2). The number of lower transistors (LT1, LT2) and the number of upper transistors (UT1, UT2) may vary depending on the embodiments. In exemplary embodiments, the upper transistors (UT1, UT2) may include string select transistors, and the lower transistors (LT1, LT2) may include ground select transistors. The gate lower lines (LL1, LL2) may each be the gate electrodes of the lower transistors (LT1, LT2). The word lines (WL) may be the gate electrodes of the memory cell transistors (MCT), and the gate upper lines (UL1, UL2) may each be the gate electrodes of the upper transist