KR-20260067839-A - DISPLAY DEVICE

Abstract

A semiconductor device according to one embodiment comprises a substrate including a cell array region and a peripheral circuit region surrounding the cell array region, an active region located in the cell array region, a plurality of word lines extending in a first direction to the peripheral circuit region while intersecting and overlapping with the active region, a plurality of bit lines extending in a second direction intersecting with the first direction while intersecting with the active region and the word lines, and a plurality of pads located in the peripheral circuit region and overlapping with the word lines, wherein in the peripheral circuit region located on one side of the cell array region, the word lines include a first word line, a second word line, a third word line, and a fourth word line, wherein the end of one or more of the first word line, the second word line, the third word line, and the fourth word line does not coincide with the end of another word line, the end of the second word line is located furthest from the cell array region, the end of the fourth word line is located closest to the cell array region, and a first pad overlapping with the first word line and a third pad overlapping with the third word line Each is positioned by shifting in a direction closer to the fourth word line from the center of the first word line and the center of the third word line.

Inventors

• 한은수
• 김병철

Assignees

• 삼성전자주식회사

Dates

Publication Date

20260513

Application Date

20241106

Claims (10)

1. A substrate comprising a cell array region and a peripheral circuit region surrounding the cell array region; An active region located in the cell array region above; A plurality of word lines extending in a first direction to the surrounding circuit area, intersecting and overlapping with the active area; A plurality of bit lines extending in a second direction that intersects the active region and the word line and intersects the first direction; and It includes a plurality of pads located in the above peripheral circuit area and overlapping with the word line, In the peripheral circuit area located on one side of the cell array area, The above word line includes a first word line, a second word line, a third word line, and a fourth word line, and The ends of one or more of the first, second, third, and fourth word lines do not coincide with the ends of other word lines, and A semiconductor device in which a first pad overlapping with the first word line and a third pad overlapping with the third word line are each positioned by shifting in a direction closer to the fourth word line from the center of the first word line and the center of the third word line, respectively.
2. In Paragraph 1, The distance in the second direction between the first pad and the third pad, where the fourth word line is located between the planes, A semiconductor device shorter than the distance in the second direction between a first pad and a third pad, where a second word line is located between the planes.
3. In Paragraph 1, A semiconductor device in which the first pad and the third pad do not overlap with the fourth word line on a plane.
4. In Paragraph 1, A semiconductor device in which the edge of the word line in the above peripheral circuit region includes a curved surface.
5. In Paragraph 1, A semiconductor device in which the edge of the word line in the above peripheral circuit region does not include a curved surface.
6. In Paragraph 1, A semiconductor device in which the ends of the first word line and the third word line are located closer to the cell array region than the end of the second word line, and are located further from the cell array region than the end of the fourth word line.
7. In Paragraph 1, A semiconductor device in which the ends of the first word line and the third word line and the end of the second word line are located on the same line in the second direction.
8. In Paragraph 1, A semiconductor device having a second pad overlapping with the second word line and a fourth pad overlapping with the fourth word line located in a peripheral circuit area located on the other side of the cell array area.
9. In paragraph 8, In the peripheral circuit area located on the other side of the cell array area, The end of the third word line is located closest to the cell array area and the first direction, and A semiconductor device in which the second pad and the fourth pad are each positioned by shifting in a direction closer to the third word line from the center of the second word line and the center of the fourth word line, respectively.
10. In Paragraph 9, The distance in the second direction between the second pad and the fourth pad, where the third word line is located in between, is A semiconductor device shorter than the distance in the second direction between the second pad and the fourth pad, where the first word line is located in between.

Description

Semiconductor device {DISPLAY DEVICE} The present invention relates to a semiconductor device. To reduce the effects of shortened channel lengths and leakage current resulting from the high integration of semiconductor devices, a buried channel array transistor (bcat) is being proposed in which the gate electrode is embedded within the semiconductor substrate and the overlapping area between the gate and drain regions is minimized. FIG. 1 is a plan view showing a semiconductor device according to one embodiment. Figure 2 is a cross-sectional view taken along the line A-A' of Figure 1. Figure 3 is a cross-sectional view taken along the line B-B' of Figure 1. Figure 4 is a cross-sectional view taken along the line C-C' of Figure 1. Figures 5 and 6 briefly illustrate the arrangement of word lines and pads in the peripheral circuit area. FIG. 7 illustrates the same area as FIG. 6 for another embodiment. FIG. 8 illustrates the same area as FIG. 6 for another embodiment. FIGS. 9 to 22 illustrate a manufacturing method according to one embodiment. Hereinafter, various embodiments of the present invention will be described in detail with reference to the attached drawings so that those skilled in the art can easily implement the present invention. The present invention may be embodied in various different forms and is not limited to the embodiments described herein. To clearly explain the present invention, parts unrelated to the explanation have been omitted, and the same reference numerals are used for identical or similar components throughout the specification. Furthermore, the size and thickness of each component shown in the drawings are depicted arbitrarily for convenience of explanation, and thus the present invention is not necessarily limited to what is illustrated. Thicknesses have been enlarged in the drawings to clearly represent various layers and regions. Additionally, for convenience of explanation, the thickness of some layers and regions has been exaggerated in the drawings. Furthermore, when it is said that a part, such as a layer, membrane, region, or plate, is "on" or "on" another part, this includes not only the case where it is "directly above" the other part, but also the case where there is another part in between. Conversely, when it is said that a part is "directly above" another part, it means that there is no other part in between. Also, saying that a part is "on" or "on" a reference part means that it is located above or below the reference part, and does not necessarily mean that it is located "on" or "on" in the direction opposite to gravity. Furthermore, throughout the specification, when a part is described as "including" a certain component, this means that, unless specifically stated otherwise, it does not exclude other components but may include additional components. Additionally, throughout the specification, "planar" means when the subject part is viewed from above, and "cross-sectional" means when the cross-section obtained by vertically cutting the subject part is viewed from the side. FIG. 1 is a plan view showing a semiconductor device according to one embodiment. FIG. 2 is a cross-sectional view taken along line A-A’ of FIG. 1. FIG. 3 is a cross-sectional view taken along line B-B’ of FIG. 1. FIG. 4 is a cross-sectional view taken along line C-C’ of FIG. 1. Referring to FIG. 1, a semiconductor device according to the present embodiment may include a cell array region (A1) and a peripheral circuit region (A2). The cell array region (A1) is a region where a plurality of memory cells are formed, and a plurality of active regions (ARs) may be located in the cell array region. The peripheral circuit region (A2) may be located to surround the cell array region, and may have devices for driving the memory cells located therein. This embodiment relates to the shape of the word line (WL) in the peripheral circuit area (A2) and its placement on the pad (PD). It is characterized by securing a margin when placing the pad (PD) by forming the word line (WL) at different lengths in the peripheral circuit area (A2). The specific placement of the peripheral circuit area (A2) will be explained separately later. Then, first, the cell array region (A1) will be described. As illustrated in FIGS. 1 to 4, a semiconductor device according to one embodiment includes an active region (AR), a word line (WL) and a bit line (BL) that intersect and overlap with the active region (AR). An active region (AR) can be defined by a device isolation layer (112) located within a substrate (100). A plurality of active regions (ARs) may be located within the substrate (100), and the plurality of active regions (ARs) are separated from each other by a device isolation layer (112). A device isolation layer (112) may be located on both sides of each active region (AR). The substrate (100) may include a semiconductor material. For example, the substrate (100) may include a group IV semiconductor, a group III-V com