KR-20260067841-A - SEMICONDUCTOR DEVICE

KR20260067841AKR 20260067841 AKR20260067841 AKR 20260067841AKR-20260067841-A

Abstract

A semiconductor device is provided, comprising a gate stack located on an active region, and contact via structures located on both sides of the gate stack in a first direction parallel to the upper surface of the active region and located between the active region and the circuit wiring, wherein the contact via structures include a gate contact via extending from the active region to the circuit wiring in a third direction perpendicular to the upper surface of the active region, a first contact insulating film covering a portion of the side of the gate contact via and exposing the remaining portion of the side, and a second contact insulating film covering a portion of the side of the first contact insulating film and exposing the remaining portion of the side, and exposing the remaining portion of the side of the gate contact via.

Inventors

신홍식
노경환
서영식
유성호
이지혜
이현철

Assignees

삼성전자주식회사

Dates

Publication Date: 20260513
Application Date: 20241106

Claims (10)

A gate stack located above the active region, and It includes a contact via structure located on both sides of the gate stack in a first direction parallel to the upper surface of the active region and located between the active region and the circuit wiring, The above contact via structure is, A gate contact via extending in a third direction perpendicular to the upper surface of the active region to the circuit wiring from the active region, A first contact insulating film covering a portion of the side of the gate contact via and exposing the remaining portion of the side, and A second contact insulating film covering a portion of the side of the first contact insulating film and exposing the remaining portion of the side, and exposing the remaining portion of the side of the gate contact via, Semiconductor device.
In Paragraph 1, The above contact via structure is, A first portion connected to the above circuit wiring and comprising the gate contact via, the first contact insulating film, and the second contact insulating film, A second portion connected to the active region and including the gate contact via, and A third portion located between the first portion and the second portion, comprising the gate contact via and the first contact insulating film, Semiconductor device.
In paragraph 2, In the first portion of the contact via structure, the first contact insulating film covers the side of the gate contact via, and the second contact insulating film covers the side of the first contact insulating film. In the third portion of the above contact via structure, the first contact insulating film covers the side of the gate contact via, and the second contact insulating film does not cover the side of the first contact insulating film, and In the second portion of the contact via structure, the first contact insulating film does not cover the side of the gate contact via, the second contact insulating film does not cover the side of the first contact insulating film, and the gate contact via is exposed. The second portion of the above contact via structure penetrates the upper surface of the active region and is inserted into the active region, and is in direct contact with the active region. Semiconductor device.
In paragraph 2, The above semiconductor device is, A fourth gate spacer located above the active region and adjacent to the first direction of the gate stack, and It further includes a first interlayer insulating film positioned on the fourth gate spacer and covering the gate stack, and The first portion of the above contact via structure is inserted into the active region by penetrating the fourth gate spacer and the upper surface of the active region, and The first contact insulating film extends in the third direction from the upper surface of the fourth gate spacer to the lower surface of the circuit wiring, Semiconductor device.
In Paragraph 4, The above semiconductor device further includes a gate spacer structure, and The above gate spacer structure is, A first gate spacer located on the side in the first direction of the gate stack, A second gate spacer located on the side of the first gate spacer in the first direction, A third gate spacer covering the first gate spacer and the second gate spacer, and It includes the fourth gate spacer located below the second gate spacer and the third gate spacer, and The first contact insulating film is in contact with a portion of the side in the first direction of the third gate spacer, and The second contact insulating film is in contact with a portion of the side of the third gate spacer in the first direction, and The second contact insulating film is in contact with a portion of the side in the first direction of the first interlayer insulating film located on the third gate spacer, Semiconductor device.
In paragraph 5, The above semiconductor device is, First and second gate stacks spaced apart in the first direction above, A first contact via structure located between the first and second gate stacks, and A second contact via structure comprising, respectively, second contact via structures located outside in the first direction of the first and second gate stacks. Semiconductor device.
In paragraph 6, The third portion of the first contact via structure is, Interposed between the third gate spacer covering the first gate stack and the third gate spacer covering the second gate stack, The third portion of the second contact via structure is, Interposed between the third gate spacer covering the first gate stack or the second gate stack and the first interlayer insulating film, Semiconductor device.
A gate stack located above the active region, and It includes a contact via structure located on both sides of the gate stack in a first direction parallel to the upper surface of the active region and located between the active region and the circuit wiring, The above contact via structure is, A first part connected to the above circuit wiring, A second part connected to the above active region, and It has a third part located between the first part and the second part, and The length of the contact via structure in the first direction has a step difference between the first part and the third part, and has a step difference between the third part and the second part. Semiconductor device.
In paragraph 8, The length in the first direction at the bottom of the first part is greater than the length in the first direction at the top of the third part. The length in the first direction at the bottom of the third part is greater than the length in the first direction at the top of the second part. Semiconductor device.
First and second gate stacks positioned above an active region and spaced apart in a first direction parallel to the upper surface of the active region, A first contact via structure located between the first and second gate stacks and between the active region and the circuit wiring, and It includes second contact via structures located respectively on the outer side in the first direction of the first and second gate stacks and located between the active region and the circuit wiring, The first contact via structure comprises a gate contact via extending in a third direction perpendicular to the upper surface of the active region from the active region to the circuit wiring, and a first contact insulating film located on the side of the gate contact via. The second contact via structure comprises a gate contact via extending in the third direction from the active region to the circuit wiring, a first contact insulating film covering a portion of the side of the gate contact via and exposing the remainder of the side, and a second contact insulating film covering a portion of the side of the first contact insulating film and exposing the remainder of the side, and exposing the remainder of the side of the gate contact via. Semiconductor device.

Description

Semiconductor Device The present disclosure relates to a semiconductor device. A semiconductor is a material that falls within the intermediate range between conductors and insulators and conducts electricity under specific conditions. Various semiconductor devices can be manufactured using such materials, such as memory devices. These semiconductor devices can be used in a wide variety of electronic devices. Due to the trend toward miniaturization and high integration of electronic devices, it is necessary to form fine patterns that constitute semiconductor devices. As the width of these fine patterns gradually decreases, the difficulty of the manufacturing process increases, which may lead to an increase in the defect rate of semiconductor devices. FIG. 1 is a plan view showing a semiconductor device according to one embodiment. FIG. 2 is a plan view showing a portion of a semiconductor device according to one embodiment. Figure 3 is a cross-sectional view along the lines A-A', B-B', and C-C' of Figure 2. Figure 4 is an enlarged cross-sectional view of part P of Figure 3. Figure 5 is an enlarged cross-sectional view of section Q of Figure 4. FIG. 6 is a cross-sectional view of a semiconductor device according to one embodiment, corresponding to FIG. 4. FIGS. 7 to 13 are drawings for explaining a method of manufacturing a semiconductor device according to one embodiment. Hereinafter, various embodiments of the present disclosure are described in detail with reference to the attached drawings so that those skilled in the art can easily implement them. The present disclosure may be embodied in various different forms and is not limited to the embodiments described herein. To clearly explain the present disclosure, parts unrelated to the description have been omitted, and the same reference numerals are used for identical or similar components throughout the specification. Furthermore, the size and thickness of each component shown in the drawings are depicted arbitrarily for convenience of explanation, and thus the present disclosure is not necessarily limited to what is illustrated. Thickness is enlarged in the drawings to clearly represent various layers and regions. Additionally, in the drawings, the thickness of some layers and regions is exaggerated for convenience of explanation. Furthermore, when a part such as a layer, membrane, region, or plate is said to be "on" or "on" another part, this includes not only the case where it is "directly above" the other part, but also the case where there is another part in between. Conversely, when a part is said to be "directly above" another part, it means that there is no other part in between. Also, being "on" or "on" a reference part means being located above or below the reference part, and does not necessarily mean being located "on" or "on" in the direction opposite to gravity. Furthermore, throughout the specification, when a part is described as "including" a certain component, this means that, unless specifically stated otherwise, it does not exclude other components but may include additional components. Additionally, throughout the specification, "planar" means when the subject part is viewed from above, and "cross-sectional" means when the cross-section obtained by vertically cutting the subject part is viewed from the side. Additionally, throughout the specification, two directions parallel to and intersecting the upper surface of the substrate are defined as the first direction (DR1) and the second direction (DR2), respectively, and a direction perpendicular to the upper surface of the substrate is described as the third direction (DR3). For example, the first direction (DR1) and the second direction (DR2) may be orthogonal to each other. FIG. 1 is a plan view showing a semiconductor device according to one embodiment. FIG. 2 is a plan view showing a portion of a semiconductor device according to one embodiment. FIG. 3 is a cross-sectional view along the lines A-A’, B-B’, and C-C’ of FIG. 2. FIG. 4 is an enlarged cross-sectional view of portion P of FIG. 3. FIG. 5 is an enlarged cross-sectional view of portion Q of FIG. 4. Referring to FIGS. 1 through 5, the semiconductor device includes a substrate (100) comprising a cell array region (CAR), a core region (COR), and a peripheral circuit region (PER). A single wafer may contain a plurality of semiconductor chips, and FIG. 1 illustrates one of the plurality of semiconductor chips. For example, the peripheral circuit area (PER) may be located on one side of the cell array area (CAR) or the core area (COR). The semiconductor chip may have a rectangular shape comprising two sides parallel to the first direction (DR1) and two sides parallel to the second direction (DR2) in a plane. The second direction (DR2) may intersect the first direction (DR1). For example, the second direction (DR2) may intersect perpendicularly to the first direction (DR1). The peripheral circuit area (PER) may have a bar shape ex