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KR-20260067849-A - POWER AMPLIFIER WITH STACK STRUCTURE AND COMMUNICATION CIRCUIT THEREOF

KR20260067849AKR 20260067849 AKR20260067849 AKR 20260067849AKR-20260067849-A

Abstract

A power amplifier circuit may include an amplifier circuit comprising a first transistor, a second transistor, and a third transistor connected in a cascode structure stacked between a power supply voltage and ground, and a bias circuit comprising a first operational amplifier and a second operational amplifier that respectively provide a first bias voltage and a second bias voltage to the first transistor and the second transistor. The first operational amplifier may include a positive input connected to a first reference voltage distributed from the power supply voltage, a negative input connected to a source node of the first transistor, an output connected to a gate node of the first transistor to provide the first bias voltage, a power node connected to the power supply voltage, and a ground node. The second operational amplifier may include a positive input connected to a second reference voltage distributed from the power supply voltage, a negative input connected to a source node of the second transistor, an output connected to a gate node of the second transistor to provide the second bias voltage, a power node connected to the ground node of the first operational amplifier, and a ground node connected to ground.

Inventors

  • 이주석
  • 이동수
  • 권대훈
  • 양성기

Assignees

  • 삼성전자주식회사

Dates

Publication Date
20260513
Application Date
20241106

Claims (20)

  1. In the power amplifier circuit (500), An amplifier circuit (522) comprising a first transistor (502), a second transistor (504), and a third transistor (506) connected in a stacked cascode structure between a power supply voltage (516) and ground; and A bias circuit (524) comprising a first operational amplifier (512) and a second operational amplifier (514) that respectively provide a first bias voltage and a second bias voltage to the first transistor and the second transistor, respectively, and The first operational amplifier comprises a positive input connected to a first reference voltage distributed from the power supply voltage, a negative input connected to the source node of the first transistor, an output connected to the gate node of the first transistor to provide the first bias voltage, a power node connected to the power supply voltage, and a ground node. The second operational amplifier is a power amplifier circuit configured to include a positive input connected to a second reference voltage distributed from the power supply voltage, a negative input connected to the source node of the second transistor, an output connected to the gate node of the second transistor to provide the second bias voltage, a power node connected to the ground node of the first operational amplifier, and a ground node connected to the ground.
  2. In Article 1, It further includes a resistor ladder comprising a first resistor (520a), a second resistor (520b), and a third resistor (520c) connected in series between the power supply voltage and the ground, and A power amplifier circuit in which the positive input of the first operational amplifier is connected between the first resistor and the second resistor, and the positive input of the second operational amplifier is connected between the second resistor and the third resistor.
  3. A power amplifier circuit according to claim 2, wherein at least one of the first resistor, the second resistor, or the third resistor is configured to have a resistance value settable according to the required gate voltage of at least one of the first transistor, the second transistor, or the third transistor.
  4. In any one of paragraphs 1 to 3, An input RF (radio frequency) signal is received through the gate node of the third transistor, and A power amplifier circuit in which an amplified output RF signal corresponding to the input RF signal is output through the drain node of the first transistor.
  5. A power amplifier circuit according to any one of claims 1 to 4, wherein the power supply voltage is provided to the drain node of the first transistor through an inductor coil.
  6. In any one of paragraphs 1 to 5, The amplifier circuit further includes at least one fourth transistor (702) connected in a cascode structure stacked on the first transistor, and The above bias circuit is a power amplifier circuit further comprising at least one operational amplifier (704) that provides a bias voltage to at least one fourth transistor.
  7. In Article 6, A power amplifier circuit further comprising a voltage regulator (708) that generates source voltages to be provided as power to the first operational amplifier and the second operational amplifier based on the above power supply voltage.
  8. In any one of paragraphs 1 to 7, The analog bias circuit further includes a mirror transistor (602) corresponding to the third transistor and a third operational amplifier (604) that provides a third bias voltage to the mirror transistor. The third operational amplifier includes a positive input connected to an analog power supply voltage, a negative input connected to the positive input of the second operational amplifier, a power node connected to the analog power supply voltage, and a ground node connected to the ground. The mirror transistor is a power amplifier circuit comprising a gate node connected to the gate node of the third transistor, a drain node connected to the analog power supply voltage, and a source node connected to ground.
  9. In any one of paragraphs 1 through 8, A power amplifier circuit in which the first transistor, the second transistor, and the third transistor are CMOS (complementary MOS (metal-oxide-semiconductor)) transistors.
  10. In any one of paragraphs 1 through 9, The above amplifier circuit is a power amplifier circuit used in the transmission path of an RF communication circuit that supports the mmWave (millimeter wave) frequency band.
  11. In a communication circuit including a transmission path, The above transmission path includes one or more power amplifiers, and at least one power amplifier (500) among the one or more power amplifiers is, An amplifier circuit (522) comprising a first transistor (502), a second transistor (504), and a third transistor (506) connected in a stacked cascode structure between a power supply voltage (516) and ground; and A bias circuit (524) comprising a first operational amplifier (512) and a second operational amplifier (514) that respectively provide a first bias voltage and a second bias voltage to the first transistor and the second transistor, respectively, and The first operational amplifier comprises a positive input connected to a first reference voltage distributed from the power supply voltage, a negative input connected to the source node of the first transistor, an output connected to the gate node of the first transistor to provide the first bias voltage, a power node connected to the power supply voltage, and a ground node. A communication circuit configured such that the second operational amplifier comprises a positive input connected to a second reference voltage distributed from the power supply voltage, a negative input connected to the source node of the second transistor, an output connected to the gate node of the second transistor to provide the second bias voltage, a power node connected to the ground node of the first operational amplifier, and a ground node connected to the ground.
  12. In claim 11, the at least one power amplifier is, It further includes a resistor ladder comprising a first resistor (520a), a second resistor (520b), and a third resistor (520c) connected in series between the power supply voltage and the ground, and A communication circuit in which the positive input of the first operational amplifier is connected between the first resistor and the second resistor, and the positive input of the second operational amplifier is connected between the second resistor and the third resistor.
  13. A communication circuit according to claim 12, wherein at least one of the first resistor, the second resistor, or the third resistor is configured to have a resistance value settable according to the required gate voltage of at least one of the first transistor, the second transistor, or the third transistor.
  14. In any one of paragraphs 11 to 13, An input RF (radio frequency) signal is received through the gate node of the third transistor, and A communication circuit in which an amplified output RF signal corresponding to the input RF signal is output through the drain node of the first transistor.
  15. A communication circuit according to any one of claims 11 to 14, wherein the power supply voltage is provided to the drain node of the first transistor through an inductor coil.
  16. In any one of Articles 11 to 15, The amplifier circuit further includes at least one fourth transistor (702) connected in a cascode structure stacked on the first transistor, and The above bias circuit is a communication circuit further comprising at least one operational amplifier (704) that provides a bias voltage to at least one fourth transistor.
  17. In claim 16, the amplifier circuit is, A communication circuit further comprising a voltage regulator (708) that generates source voltages to be supplied as power to the first operational amplifier and the second operational amplifier based on the above power supply voltage.
  18. In any one of Articles 11 through 17, The analog bias circuit further includes a mirror transistor (602) corresponding to the third transistor and a third operational amplifier (604) that provides a third bias voltage to the mirror transistor. The third operational amplifier includes a positive input connected to an analog power supply voltage, a negative input connected to the positive input of the second operational amplifier, a power node connected to the analog power supply voltage, and a ground node connected to the ground. The above mirror transistor is a communication circuit comprising a gate node connected to the gate node of the third transistor, a drain node connected to the analog power supply voltage, and a source node connected to ground.
  19. In any one of paragraphs 11 through 18, A communication circuit in which the first transistor, the second transistor, and the third transistor are CMOS (complementary MOS (metal-oxide-semiconductor)) transistors.
  20. In any one of Articles 11 through 19, The above-mentioned transmitting circuit is a communication circuit configured to support the mmWave (millimeter wave) frequency band.

Description

Power amplifier with stack structure and communication circuit thereof The embodiments of the present disclosure relate to a power amplifier with a stack structure and a communication circuit thereof. To meet the increasing demand for wireless data traffic following the 4G system (i.e., the LTE (long-term evolution) system), 5G systems have been developed and commercialized. 5G systems can be implemented in the millimeter wave (mmWave) band. To mitigate path loss and increase the transmission distance of radio waves in the millimeter wave band, beamforming, massive array multiple input/output (massive MIMO), full-dimensional multiple input/output (Full Dimensional MIMO: FD-MIMO), array antenna, analog beamforming, and large-scale antenna technologies are being discussed for 5G systems. In a base station of a MIMO-based 5G system using the mmWave band, single or multiple beams can be formed through an array antenna and used for communication. The base station can improve communication quality by focusing signals from each direction of one or more user equipment (UE) through beamforming that forms single or multiple beams. With the advancement of technologies such as the Internet of Things (IoT), cloud computing, and big data, and the increasing public data consumption, the demand for high-capacity wireless communication technology is surging. Existing frequency bands have already reached saturation with various communication services, and limited bandwidth makes it difficult to provide higher data transmission speeds. Therefore, implementing high-capacity wireless communication technology requires signal processing in higher frequency bands. High frequency bands, such as mmWave (millimeter wave) bands higher than 10 GHz, can significantly improve data transmission speeds based on wide bandwidth and avoid congestion in low frequency bands, thereby enabling the provision of high-quality communication services. However, mmWave bands have the problem of high signal loss and can be easily blocked by obstacles. To overcome the aforementioned problems, research on beamforming, increasing cell density, and high-power amplifiers is actively underway. High-power amplifiers amplify the strength of output signals to extend communication distance and provide a stable connection. CMOS (complementary MOSFET (metal-oxide-semiconductor field-effect transistor))-based power amplifiers are inexpensive and have very high integration density, making it easy to implement beamforming technology at high frequencies. However, compared to other compound semiconductors (e.g., GaAs (gallium arsenide) or GaN (gallium nitride)), the usable power is low, and it may be difficult to provide high output power. The information described above may be provided as related art for the purpose of aiding understanding of the present disclosure. No claim or determination is made as to whether any of the foregoing may be applied as prior art related to the present disclosure. In relation to the description of the drawings, the same or similar reference numerals may be used for identical or similar components. FIG. 1 is a block diagram of an electronic device in a network environment according to various embodiments. FIG. 2a shows the basic structure of a power amplifier according to one embodiment of the present disclosure. FIG. 2b shows a stack structure of a power amplifier according to one embodiment of the present disclosure. FIG. 3 shows an operational amplifier-based bias circuit for a two-stack power amplifier according to one embodiment of the present disclosure. FIG. 4 shows an operational amplifier-based bias circuit for a 3-stack power amplifier according to one embodiment of the present disclosure. FIG. 5 shows a bias circuit including stacked operational amplifiers according to one embodiment of the present disclosure. FIG. 6 shows a power amplifier circuit including a bias circuit of a stacked operational amplifier structure according to one embodiment of the present disclosure. FIG. 7 shows a power amplifier circuit including a bias circuit of a multi-stacked operational amplifier structure according to one embodiment of the present disclosure. Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. In describing the embodiments of the present disclosure, specific descriptions of related known functions or configurations are omitted if it is determined that such detailed descriptions would unnecessarily obscure the essence of the present disclosure. Furthermore, terms used below are defined considering their functions in the embodiments of the present disclosure, and these may vary depending on the intent or practice of the user or operator. Therefore, such definitions should be based on the content throughout the present disclosure. It should be noted that technical terms used in this disclosure are used merely to describe one embodiment and are not intended to limit this di