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KR-20260067891-A - SEMICONDUCTOR DEVICE

KR20260067891AKR 20260067891 AKR20260067891 AKR 20260067891AKR-20260067891-A

Abstract

The present disclosure relates to a semiconductor device, wherein a semiconductor device according to one embodiment comprises a substrate, a bit line extending in a first direction located on the substrate, a plurality of word lines extending along a second direction intersecting the first direction, a first active pattern and a second active pattern located between the plurality of word lines and spaced apart along the first direction, a cell capacitor located on the first active pattern and the second active pattern, and a plurality of shield gates located at a level between the plurality of word lines and the cell capacitor, wherein each of the first active pattern and the second active pattern comprises a first dopant region connected to the bit line, a second dopant region connected to the cell capacitor, and a channel region located between the first dopant region and the second dopant region, and the plurality of shield gates overlap at least one of the second dopant regions among the first active pattern and the second active pattern in the first direction.

Inventors

  • 정문영
  • 이상호
  • 최재현

Assignees

  • 삼성전자주식회사

Dates

Publication Date
20260513
Application Date
20241106

Claims (10)

  1. substrate, A bit line located on the above substrate and extending in a first direction, A plurality of word lines extending along a second direction intersecting the first direction, A first active pattern and a second active pattern located between the plurality of word lines and spaced apart along the first direction, A cell capacitor positioned above the first active pattern and the second active pattern, and It includes a plurality of shield gates located at a level between the plurality of word lines and the cell capacitor, and Each of the above first active pattern and second active pattern is, A first dopant region connected to the above bit line, A second dopant region connected to the cell capacitor, and It includes a channel region located between the first dopant region and the second dopant region, and A semiconductor device in which the plurality of shield gates overlap at least one second dopant region among the first active pattern and the second active pattern in the first direction.
  2. In Paragraph 1, A semiconductor device in which the plurality of shield gates overlap the plurality of word lines in a vertical direction.
  3. In Paragraph 1, Located between the first active pattern and the second active pattern, A semiconductor device further comprising a back gate electrode extending along the second direction.
  4. In Paragraph 3, The above plurality of shield gates are, A first shield gate overlapping in a vertical direction with the back gate electrode, and A semiconductor device comprising a second shield gate that overlaps the above plurality of word lines in a vertical direction.
  5. In Paragraph 4, Different voltages are applied to the back gate electrode and the first shield gate, and A semiconductor device in which different voltages are applied to the plurality of word lines and the second shield gate.
  6. A substrate including a cell array region and a peripheral circuit region, A bit line located above the cell array area and extending in a first direction, A plurality of word lines extending along a second direction intersecting the first direction, A first active pattern and a second active pattern located between the plurality of word lines and spaced apart along the first direction, A back gate electrode located between the first active pattern and the second active pattern and extending along the second direction, A cell capacitor positioned above the first active pattern and the second active pattern, and It includes a plurality of shield gates that overlap in a vertical direction with at least one of the plurality of word lines and the back gate electrode, and Each of the above first active pattern and second active pattern is, A first dopant region connected to the above bit line, A second dopant region connected to the cell capacitor, and It includes a channel region located between the first dopant region and the second dopant region, and A semiconductor device in which the plurality of shield gates overlap at least one second dopant region among the first active pattern and the second active pattern in the first direction.
  7. In Paragraph 6, The above plurality of shield gates are, A first shield gate overlapping in a vertical direction with the back gate electrode, and A semiconductor device comprising a second shield gate that overlaps the above plurality of word lines in a vertical direction.
  8. In Paragraph 7, A semiconductor device in which the width of the first shield gate and the width of the second shield gate are different.
  9. In Paragraph 7, A semiconductor device in which the thickness of the first shield gate and the thickness of the second shield gate are different.
  10. A substrate including a cell array region and a peripheral circuit region, A peripheral circuit structure comprising a peripheral circuit located on the substrate and peripheral circuit wiring connected to the peripheral circuit, and It includes a cell structure that overlaps the above peripheral circuit structure in a vertical direction, and The above cell structure is, A bit line located on the above substrate and extending in a first direction, A plurality of word lines extending along a second direction intersecting the first direction, A plurality of active patterns located between the plurality of word lines and spaced apart along the first direction, A back gate electrode located between the plurality of active patterns and extending in the second direction, A cell capacitor located on the above plurality of active patterns, A first shield gate overlapping the above back gate electrode and the above vertical direction, and It includes a second shield gate that overlaps the plurality of word lines in a vertical direction, and Each of the multiple active patterns is, A first dopant region connected to the above bit line, A second dopant region connected to the cell capacitor, and It includes a channel region located between the first dopant region and the second dopant region, and A semiconductor device in which each of the first shield gate and the second shield gate overlaps with the second dopant region in the first direction.

Description

Semiconductor Device The present disclosure relates to a semiconductor device. Technology is required to increase the integration density of semiconductor devices. In the case of two-dimensional semiconductor devices, the integration density is primarily determined by the area occupied by a unit memory cell, and the integration density in this aspect can be influenced by the level of fine pattern formation technology. However, since fine pattern formation technology requires expensive equipment, the integration density of 2D semiconductor devices is increasing but remains limited. Accordingly, 3D semiconductor memory devices equipped with memory cells arranged in 3D are being proposed. As the components included in three-dimensional semiconductor memory devices become more integrated and miniaturized, it is important to minimize the influence between the components included in the semiconductor devices in order to improve the operational performance of the semiconductor devices. FIG. 1 is a plan view of a semiconductor device according to one embodiment. FIG. 2 is a plan view showing a part of the configuration of a semiconductor device according to one embodiment. Figure 3 is a plan view showing a part of the configuration of Figure 2. Figure 4 is a cross-sectional view showing a cross-section cut along the lines A-A' and B-B' of Figure 1. Figure 5 is a cross-sectional view showing a cross-section cut along the line C-C' of Figure 1. Figure 6 is a cross-sectional view showing a cross-section cut along the D-D' and E-E' lines of Figure 1. Figure 7 is a magnified view of the P1 area of Figure 5. FIGS. 8 to 17 are cross-sectional views illustrating cross-sections of semiconductor devices according to some embodiments. FIGS. 18 and 19 are plan views showing some configurations of a semiconductor device according to some embodiments. FIG. 21 is a cross-sectional view showing a cross- section of a semiconductor device according to some embodiments. Figure 22 is an enlarged view of the R1 region of Figure 21. FIGS. 23 and 24 are cross-sectional views illustrating cross-sections of a semiconductor device according to some embodiments. FIGS. 25 to 33 are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment. Hereinafter, various embodiments of the present invention will be described in detail with reference to the attached drawings so that those skilled in the art can easily implement the present invention. The present invention may be embodied in various different forms and is not limited to the embodiments described herein. To clearly explain the present invention, parts unrelated to the explanation have been omitted, and the same reference numerals are used for identical or similar components throughout the specification. Furthermore, the size and thickness of each component shown in the drawings are depicted arbitrarily for convenience of explanation, and thus the present invention is not necessarily limited to what is illustrated. Thicknesses have been enlarged in the drawings to clearly represent various layers and regions. Additionally, for convenience of explanation, the thickness of some layers and regions has been exaggerated in the drawings. Furthermore, when it is said that a part, such as a layer, membrane, region, or plate, is "on" or "on" another part, this includes not only the case where it is "directly above" the other part, but also the case where there is another part in between. Conversely, when it is said that a part is "directly above" another part, it means that there is no other part in between. Also, saying that a part is "on" or "on" a reference part means that it is located above or below the reference part, and does not necessarily mean that it is located "on" or "on" in the direction opposite to gravity. Furthermore, throughout the specification, when a part is described as "including" a certain component, this means that, unless specifically stated otherwise, it does not exclude other components but may include additional components. Additionally, throughout the specification, "planar" means when the subject part is viewed from above, and "cross-sectional" means when the cross-section obtained by vertically cutting the subject part is viewed from the side. Hereinafter, a semiconductor device according to one embodiment will be described with reference to FIGS. 1 to 7. FIG. 1 is a plan view of a semiconductor device according to one embodiment. FIG. 2 is a plan view showing a partial configuration of a semiconductor device according to one embodiment. FIG. 3 is a plan view showing a partial configuration of FIG. 2. FIG. 4 is a cross-sectional view showing a cross section cut along the lines A-A’ and B-B’ of FIG. 1. FIG. 5 is a cross-sectional view showing a cross section cut along the line C-C’ of FIG. 1. FIG. 6 is a cross-sectional view showing a cross section cut along the lines D-D’ and E-E’ of FIG. 1. FIG. 7 is a partial en