KR-20260067952-A - Integrated semiconductor device based on Diamond and nitride including heat dissipation layer, and method of manufacturing

KR20260067952AKR 20260067952 AKR20260067952 AKR 20260067952AKR-20260067952-A

Abstract

The present invention relates to a diamond and nitride-based semiconductor integrated device including a heat dissipation layer and a method for manufacturing such a device, and more specifically, to a method for manufacturing a semiconductor integrated device applicable to an electrical circuit including a CMOS circuit by forming a p-type diamond FET utilizing 2 DHG channels and an n-type nitride FET utilizing 2 DEG channels on a single substrate layer and electrically connecting them, which corresponds to a method for manufacturing a high-voltage, high-frequency semiconductor device utilizing the wide bandgap characteristics of diamond and nitride, and which prevents device degradation by utilizing the excellent heat dissipation characteristics of diamond and can manufacture a high-reliability semiconductor device.

Inventors

남옥현
유근호
곽태명
정주철

Assignees

한국공학대학교산학협력단

Dates

Publication Date: 20260513
Application Date: 20250324
Priority Date: 20241106

Claims (14)

As a nitride and diamond-based semiconductor integrated device, It includes a substrate layer; a nitride FET formed in a portion of the substrate layer; and a diamond FET formed in another portion of the substrate layer. The above nitride FET is, A first multilayer comprising a plurality of layers made of aluminum gallium nitride (Al x Ga 1-x N) with different detailed compositions; A first insulating layer disposed on the first multilayer above; and Includes a first electrode; and The above diamond FET is, A second multilayer comprising a plurality of layers made of aluminum gallium nitride (Al x Ga 1-x N) with different detailed compositions; A second insulating layer disposed on the second multilayer above; A second diamond layer disposed on the second insulating layer; and A second electrode formed on the second diamond layer; comprising The above semiconductor integrated device is a semiconductor integrated device that forms an integrated circuit by electrically connecting the first electrode and the second electrode.
In claim 1, The first multilayer of the above nitride FET is, First buffer layer; A first channel layer disposed on the first buffer layer above; A first barrier layer disposed on the first channel layer; and A first capping layer disposed on the first barrier layer; comprising The second multilayer of the above diamond FET is, Second buffer layer; A second channel layer disposed on the second buffer layer above; A second barrier layer disposed on the second channel layer; and A semiconductor integrated device comprising: a second capping layer disposed on the second barrier layer.
In claim 2, The first buffer layer, first channel layer, first barrier layer, and first capping layer of the nitride FET each comprise aluminum gallium nitride represented by the chemical formula Al x Ga 1-x N, and The aluminum gallium nitride (Al x Ga 1-x N) included in each of the two layers arranged adjacent to each other among the first channel layer, the first barrier layer, and the first capping layer has different x values, and The x value of the aluminum gallium nitride (Al x Ga 1-x N) included in the first channel layer is smaller than the x value of the aluminum gallium nitride (Al x Ga 1-x N) included in the first barrier layer, and The second buffer layer, second channel layer, second barrier layer, and second capping layer of the diamond FET each comprise aluminum gallium nitride represented by the chemical formula Al x Ga 1-x N, and The aluminum gallium nitride (Al x Ga 1-x N) included in each of the two layers arranged adjacent to each other among the second channel layer, the second barrier layer, and the second capping layer has different x values, and The x value of the aluminum gallium nitride (Al x Ga 1-x N) included in the second channel layer is smaller than the x value of the aluminum gallium nitride (Al x Ga 1-x N) included in the second barrier layer, and A semiconductor integrated device in which the x value of the aluminum gallium nitride (Al x Ga 1-x N) included in each of the nitride FET and the diamond FET is 0.1 to 99.9.
In claim 1, The above nitride FET is, A semiconductor integrated device further comprising a first diamond layer disposed on the first insulating layer.
In claim 2, The first electrode of the above nitride FET is, A semiconductor integrated device formed by etching a portion of the first insulating layer and depositing a metal on the exposed first capping layer.
In claim 1, A semiconductor integrated device wherein the first insulating layer and the second insulating layer each comprise one or more of SiN y and SiO 2 .
In claim 1, The above diamond FET further comprises an oxide film layer formed on the second diamond layer, and A semiconductor integrated device comprising one or more of Al₂O₃ , SiO₂ , HfO₂ , MoO₃ , V₂O₅ , and WO₃ , wherein the oxide film layer comprises
In claim 4, The first diamond layer is formed by applying a diamond seed on the first insulating layer and growing it by chemical vapor deposition (CVD) at a growth rate of 0.01 to 1000 μm/hr under conditions of a pressure of 0 to 1000 torr and a temperature of 100 to 1500°C. A semiconductor integrated device, wherein the second diamond layer is formed by applying a diamond seed on the second insulating layer and growing it by chemical vapor deposition (CVD) at a growth rate of 0.01 to 1000 μm/hr under conditions of a pressure of 0 to 1000 torr and a temperature of 100 to 1500°C.
In claim 2, The above substrate layer is any one of Al₂O₃ , Si, SiC, and nitride-based substrates, and A semiconductor integrated device, wherein the first buffer layer, the second buffer layer, the first channel layer, the second channel layer, the first barrier layer, the second barrier layer, the first capping layer, and the second capping layer are each formed at a growth rate of 0.01 to 1000 μm/hr under conditions of a pressure of 0 to 1000 torr and a temperature of 400 to 1500℃.
In claim 2, The first electrode comprises a first source, a first gate formed spaced apart from the first source, and a first drain formed spaced apart from the first source and the first gate. The above nitride FET is, A semiconductor integrated device further comprising a p-aluminum gallium nitride layer formed between the first gate and the first capping layer.
In claim 2, The first electrode comprises a first source, a first gate formed spaced apart from the first source, and a first drain formed spaced apart from the first source and the first gate. The above nitride FET is, It further includes an oxide film layer formed between the first gate and the first capping layer, and The oxide film layer comprises one or more of Al₂O₃ , SiO₂ , HfO₂ , MoO₃ , V₂O₅ , and WO₃ , Semiconductor integrated circuit.
A method for manufacturing nitride and diamond-based semiconductor integrated devices, Substrate layer preparation step for preparing a substrate layer; A nitride FET formation step for forming a nitride FET in a portion of the substrate layer; and a diamond FET formation step for forming a diamond FET in another portion of the substrate layer; are included. The above nitride FET formation step is, A first multilayer forming step comprising a plurality of layers made of aluminum gallium nitride (Al x Ga 1-x N) having different detailed compositions; A first insulating layer placement step of placing a first insulating layer on the first multilayer above; and Includes a first electrode formation step; and The above diamond FET formation step is, A second multilayer forming step comprising a plurality of layers made of aluminum gallium nitride (Al x Ga 1-x N) with different detailed compositions; A second insulating layer placement step of placing a second insulating layer on the second multilayer above; A second diamond layer placement step of placing a second diamond layer on the second insulating layer; and A second electrode forming step of forming a second electrode on the second diamond layer; comprising A method for manufacturing a semiconductor integrated device, wherein the semiconductor integrated device electrically connects the first electrode and the second electrode to form an integrated circuit.
In claim 12, The above nitride FET formation step is, A method for manufacturing a semiconductor integrated device, further comprising a first diamond layer placement step of placing a first diamond layer on the first insulating layer.
In claim 12, The above first multilayer formation step is, First buffer layer placement step; A first channel layer placement step of placing a first channel layer on the first buffer layer; A first barrier layer placement step of placing a first barrier layer on the first channel layer; and A first capping layer placement step of placing a first capping layer on the first barrier layer; The above second multilayer formation step is, Second buffer layer placement step; A second channel layer placement step of placing a second channel layer on the second buffer layer; A second barrier layer placement step of placing a second barrier layer on the second channel layer; and A method for manufacturing a semiconductor integrated device, comprising: a second capping layer placement step of placing a second capping layer on the second barrier layer.

Description

Integrated semiconductor device based on diamond and nitride including heat dissipation layer and method of manufacturing The present invention relates to a diamond and nitride-based semiconductor integrated device including a heat dissipation layer and a method for manufacturing thereof, and more specifically, to a semiconductor integrated device including a heat dissipation layer and a method for manufacturing thereof, wherein a p-type diamond FET utilizing 2DHG channels and an n-type nitride FET utilizing 2DEG channels are formed on a single substrate layer and electrically connected to provide a semiconductor integrated device applicable to an electrical circuit including a CMOS circuit. CMOS (complementary metal-oxide semiconductor) is a semiconductor device manufactured such that P-channel FETs and N-channel FETs are placed adjacently on a single chip, with the gates of the P-channel FETs and N-channel FETs connected to the inputs and the drains connected to the outputs, allowing the two FETs to operate complementarily. CMOS has the advantage of low power consumption and is used as a switching device in most logic circuits. Conventional CMOS devices were mostly based on silicon (Si), but as device miniaturization progressed, problems such as increased power consumption and heat generation occurred. In addition, due to the characteristics of silicon, conventional silicon-based CMOS devices have the problem of being difficult to utilize as ultra-high voltage and ultra-high frequency devices. However, the electric vehicle, 5G, and aerospace sectors, where the market is currently expanding rapidly, require semiconductor devices capable of operating in high-voltage, high-temperature, and high-frequency environments. Accordingly, there is a demand for new semiconductor devices to replace silicon-based devices. In other words, there is a demand for semiconductor devices and manufacturing technologies that possess excellent withstand voltage characteristics, can prevent device degradation due to high temperatures, and can operate in extreme environments such as space. FIG. 1 illustrates a schematic diagram of a semiconductor integrated circuit according to one embodiment of the present invention. FIG. 2 schematically illustrates a method for manufacturing a semiconductor integrated circuit according to one embodiment of the present invention. FIG. 3 schematically illustrates a nitride FET formation step according to one embodiment of the present invention. FIG. 4 schematically illustrates the first multilayer formation step of the nitride FET formation step according to one embodiment of the present invention. FIG. 5 schematically illustrates a diamond FET formation step according to one embodiment of the present invention. FIG. 6 schematically illustrates the second multilayer formation step of the diamond FET formation step according to one embodiment of the present invention. FIG. 7 schematically illustrates the structure of a semiconductor integrated device including an oxide film layer according to one embodiment of the present invention. FIG. 8 schematically illustrates the process of forming a two-dimensional hole gas according to one embodiment of the present invention. FIG. 9 schematically illustrates the process of forming a two-dimensional electron gas according to one embodiment of the present invention. FIG. 10 schematically illustrates a diamond FET according to one embodiment of the present invention and the voltage-current characteristics of the diamond FET. FIG. 11 schematically illustrates a semiconductor integrated device and the voltage-drain current characteristics of the semiconductor integrated device according to one embodiment of the present invention. FIG. 12 schematically illustrates the structure of a semiconductor integrated device further comprising a p-aluminum nitride gallium layer according to one embodiment of the present invention. FIG. 13 schematically illustrates the structure of a semiconductor integrated device further comprising an oxide film layer according to one embodiment of the present invention. Hereinafter, various embodiments and/or aspects are disclosed with reference to the drawings. For illustrative purposes, numerous specific details are disclosed in the following description to aid in a general understanding of one or more aspects. However, it will also be recognized by those skilled in the art that these aspects may be practiced without such specific details. The following description and the accompanying drawings describe specific exemplary aspects of one or more aspects in detail. However, these aspects are exemplary, and some of the various methods in the principles of the various aspects may be used, and the description is intended to include all such aspects and their equivalents. In addition, various aspects and features will be presented by a system that may include a number of devices, components and/or modules, etc. It should also be understood an