KR-20260067953-A - Integrated Semiconductor Device Based on Diamond and Nitride Including Metal Buffer Layer, and Method of Manufacturing

KR20260067953AKR 20260067953 AKR20260067953 AKR 20260067953AKR-20260067953-A

Abstract

The present invention relates to a diamond and nitride-based semiconductor integrated device comprising a metal buffer layer and a method for manufacturing thereof. More specifically, it provides a semiconductor integrated device with improved heat dissipation performance and charge mobility by forming a nitride semiconductor device and a diamond semiconductor device on a single substrate layer. This corresponds to a method for fabricating high-voltage, high-frequency semiconductor devices utilizing the wide bandgap characteristics of diamond and nitride, and enables the fabrication of high-reliability semiconductor devices by preventing device degradation through the excellent heat dissipation characteristics of diamond.

Inventors

남옥현
유근호
곽태명
정주철

Assignees

한국공학대학교산학협력단

Dates

Publication Date: 20260513
Application Date: 20250324
Priority Date: 20241106

Claims (11)

As a semiconductor integrated device, A substrate layer; a nitride semiconductor device formed on the substrate layer; and a diamond semiconductor device; are included. The above nitride semiconductor device is, A buffer layer disposed on the above substrate layer; A channel layer disposed on the above buffer layer; A barrier layer disposed on the above channel layer; A capping layer disposed on the above barrier layer; and A first electrode disposed on the capping layer; comprising The above diamond semiconductor device is, A metal buffer layer disposed on the above substrate layer; A diamond layer disposed on the metal buffer layer above; A second electrode disposed on the diamond layer; comprising The above semiconductor integrated device is a semiconductor integrated device that forms an integrated circuit by electrically connecting the first electrode and the second electrode.
In claim 1, A semiconductor integrated device comprising any one of Si, Al₂O₃ , SiC, GaN, AlN, and Ga₂O₃ , wherein the substrate layer is a semiconductor integrated device.
In claim 1, The above nitride semiconductor device comprises one or more of gallium nitride (GaN), aluminum nitride (AlN), and aluminum gallium nitride (Al x Ga 1-x N), and A semiconductor integrated device in which the x value of the aluminum gallium nitride represented by the chemical formula Al x Ga 1-x N is 0.1 to 99.9.
In claim 3, In the case where the above nitride semiconductor device includes the above aluminum gallium nitride (Al x Ga 1-x N), The aluminum gallium nitride (Al x Ga 1-x N) contained in each of the two adjacent layers among the channel layer, barrier layer, and capping layer has different x values, and A semiconductor integrated device in which the x value of aluminum gallium nitride (Al x Ga 1-x N) included in the channel layer is smaller than the x value of aluminum gallium nitride (Al x Ga 1-x N) included in the barrier layer.
In claim 1, The above substrate layer is any one of Al₂O₃ , Si, SiC, and nitride-based substrates, and The above nitride semiconductor device is a semiconductor integrated device formed at a growth rate of 0.01 to 1000 μm/hr under conditions of a pressure of 0 to 1000 torr and a temperature of 400 to 1500℃.
In claim 1, The above metal buffer layer comprises one or more of iridium (Ir), ruthenium (Ru), Al₂O₃ , YSZ, and SrTiO₃ , forming a semiconductor integrated device.
In claim 1, The above diamond semiconductor device is formed by chemical vapor deposition (CVD), and The above substrate layer comprises one or more of Al₂O₃ , MgO , Si, SiC, and nitride-based substrates, and A semiconductor integrated device in which the diamond layer is formed at a growth rate of 0.01 to 1000 μm/hr under conditions of a pressure of 0 to 1000 torr and a temperature of 100 to 1500℃.
In claim 1, The above diamond semiconductor device is, It further includes an oxide film layer disposed on the diamond layer above, and The above second electrode is a semiconductor integrated device disposed on the oxide film layer.
In claim 1, The first electrode comprises a first source, a first gate formed spaced apart from the first source, and a first drain formed spaced apart from the first source and the first gate. The above nitride semiconductor device is, A semiconductor integrated device further comprising a p-gallium aluminum nitride layer formed between the first gate and the capping layer.
In claim 1, The second electrode comprises a second source, a second gate formed spaced apart from the second source, and a second drain formed spaced apart from the second source and the second gate. The above diamond semiconductor device is, n-diamond layer formed on the above diamond layer; A p-diamond layer formed between the n-diamond layer and the second source, and between the n-diamond layer and the second drain, respectively; and A semiconductor integrated device further comprising an oxide film layer formed between the n-diamond layer and the second gate.
As a method for manufacturing a semiconductor integrated device, Substrate layer preparation step for preparing a substrate layer; A step of forming a nitride semiconductor device on the substrate layer; and A diamond semiconductor device formation step for forming a diamond semiconductor device on the substrate layer; comprising The above nitride semiconductor device formation step is, A buffer layer placement step of placing a buffer layer on the substrate layer; A channel layer placement step of placing a channel layer on the above buffer layer; A barrier layer placement step of placing a barrier layer on the above channel layer; A capping layer placement step of placing a capping layer on the above barrier layer; and A first electrode placement step of placing a first electrode on the capping layer; comprising, The above diamond semiconductor device formation step is, A metal buffer layer placement step of placing a metal buffer layer on the above substrate layer; A diamond layer placement step of placing a diamond layer on the metal buffer layer above; and A second electrode placement step of placing a second electrode on the diamond layer; comprising A method for manufacturing a semiconductor integrated device, wherein the semiconductor integrated device electrically connects the first electrode and the second electrode to form an integrated circuit.

Description

Integrated Semiconductor Device Based on Diamond and Nitride Including Metal Buffer Layer, and Method of Manufacturing The present invention relates to a diamond and nitride-based semiconductor integrated device comprising a metal buffer layer and a method for manufacturing thereof, and more specifically, to a semiconductor integrated device having improved heat dissipation performance and charge mobility by forming a nitride semiconductor device and a diamond semiconductor device on a single substrate layer. CMOS (complementary metal-oxide semiconductor) is a semiconductor device manufactured such that P-channel FETs and N-channel FETs are placed adjacently on a single chip, with the gates of the P-channel FETs and N-channel FETs connected to the inputs and the drains connected to the outputs, allowing the two FETs to operate complementarily. CMOS has the advantage of low power consumption and is used as a switching device in most logic circuits. Conventional CMOS devices were mostly based on silicon (Si), but as device miniaturization progressed, problems such as increased power consumption and heat generation occurred. In addition, due to the characteristics of silicon, conventional silicon-based CMOS devices have the problem of being difficult to utilize for high-speed switching, ultra-high voltage, and ultra-high frequency devices. However, the electric vehicle, 5G, and aerospace sectors, where the market is currently expanding rapidly, require semiconductor devices capable of operating in high-voltage, high-temperature, and high-frequency environments with improved switching characteristics. Accordingly, there is a demand for new semiconductor devices to replace silicon-based devices. In other words, there is a demand for semiconductor devices and manufacturing technologies that possess excellent withstand voltage characteristics, enable high-speed switching, prevent device degradation due to high temperatures, and operate in extreme environments such as space. FIG. 1 illustrates a schematic diagram of a semiconductor integrated circuit according to one embodiment of the present invention. FIG. 2 schematically illustrates a method for manufacturing a semiconductor integrated circuit according to one embodiment of the present invention. FIG. 3 schematically illustrates a step for forming a nitride semiconductor device according to one embodiment of the present invention. FIG. 4 schematically illustrates a diamond semiconductor device formation step according to one embodiment of the present invention. FIG. 5 schematically illustrates the structure of a semiconductor integrated device including an oxide film layer according to one embodiment of the present invention. FIG. 6 schematically illustrates the process of forming a two-dimensional hole gas according to one embodiment of the present invention. FIG. 7 schematically illustrates the process of forming a two-dimensional electron gas according to one embodiment of the present invention. FIG. 8 schematically illustrates the structure of a semiconductor integrated device further comprising an oxide film layer and a doped diamond multilayer structure according to one embodiment of the present invention. FIG. 9 schematically illustrates the structure of a semiconductor integrated device further comprising a p-aluminum gallium nitride layer and a doped diamond multilayer structure according to one embodiment of the present invention. FIG. 10 schematically illustrates the structure of a semiconductor integrated device further comprising a p-aluminum nitride gallium layer (2410) according to one embodiment of the present invention. Hereinafter, various embodiments and/or aspects are disclosed with reference to the drawings. For illustrative purposes, numerous specific details are disclosed in the following description to aid in a general understanding of one or more aspects. However, it will also be recognized by those skilled in the art that these aspects may be practiced without such specific details. The following description and the accompanying drawings describe specific exemplary aspects of one or more aspects in detail. However, these aspects are exemplary, and some of the various methods in the principles of the various aspects may be used, and the description is intended to include all such aspects and their equivalents. In addition, various aspects and features will be presented by a system that may include multiple devices, components and/or modules, etc. It should also be understood and recognized that various systems may include additional devices, components and/or modules, etc., and/or may not include all of the devices, components, modules, etc. discussed in relation to the drawings. As used herein, terms such as "examples," "examples," "aspects," "examples," etc., may not be interpreted as implying that any aspect or design described is better or more advantageous than other aspects or designs. Additionally, the terms “comprising” and/or “c