KR-20260067962-A - INTEGRATED CIRCUIT DEVICES INCLUDING STACKED TRANSISTORS WITH MATCHED WORK FUNCTION SCHEME AND METHODS OF FABRICATION THE SAME

Abstract

Integrated circuit devices and methods for manufacturing the same are provided. The integrated circuit devices include a first transistor on a substrate and a second transistor on the first transistor, wherein the first transistor is located between the substrate and the second transistor in a vertical direction perpendicular to the upper surface of the substrate, and the first transistor includes first channel layers spaced apart from each other in the vertical direction; and a first work function layer on the first channel layers, and the second transistor includes second channel layers spaced apart from each other in the vertical direction; and a second work function layer on the second channel layers, wherein the second work function layer is spaced apart from the first channel layers.

Inventors

• 박준모
• 서강일

Assignees

• 삼성전자주식회사

Dates

Publication Date

20260513

Application Date

20250605

Priority Date

20250430

Claims (20)

1. A first transistor on a substrate; and A second transistor on the first transistor, wherein The first transistor is positioned between the substrate and the second transistor in a vertical direction perpendicular to the upper surface of the substrate, and The first transistor above is: First channel layers spaced apart from each other in the vertical direction above; and It includes a first work function layer on the first channel layers, and The second transistor above is: Second channel layers spaced apart from each other in the vertical direction above; and It includes a second work function layer on the second channel layers above, and The above second work function layer is an integrated circuit device spaced apart from the above first channel layers.
2. In Article 1, The first work function layer is an integrated circuit device located between the first channel layers and the second work function layer.
3. In Article 2, The above second work function layer includes a second inner work function layer and a second outer work function layer, and The second internal work function layer is located between adjacent second channel layers among the second channel layers, and The second external work function layer extends around the second channel layers and the second internal work function layer, and The second work function layer is an integrated circuit device having an interface between the second internal work function layer and the second external work function layer.
4. In Paragraph 3, The first work function layer includes a first internal work function layer and a first external work function layer, and The first internal work function layer is located between adjacent first channel layers among the first channel layers, and The first external work function layer extends around the first channel layers and the first internal work function layer, and An integrated circuit device in which the first work function layer does not have an interface between the first internal work function layer and the first external work function layer.
5. In Article 4, An integrated circuit device configured such that the first internal work function layer and the first external work function layer form an integrated structure.
6. In Article 4, The interface of the second work function layer is an integrated circuit device that overlaps the second channel layers in the vertical direction.
7. In Article 6, An integrated circuit device in which, in a horizontal direction parallel to the upper surface of the substrate, the width of at least one of the second channel layers is greater than the width of the second internal work function layer.
8. In Article 6, The first internal work function layer and the first external work function layer are an integrated circuit device comprising a first material.
9. In Article 8, An integrated circuit device comprising the second internal work function layer and the second external work function layer, wherein the second internal work function layer comprises a second material different from the first material.
10. In Article 8, The above second internal work function layer includes a second material, The above second external work function layer includes a third material, and The above second material is an integrated circuit device different from the above first material and the above third material.
11. A first transistor on a substrate; A second transistor on the first transistor above; and It includes an insulator located between the first transistor and the second transistor in a vertical direction perpendicular to the upper surface of the substrate, The first transistor above is: First channel layers spaced apart from each other in the vertical direction above; and It includes a first work function layer on the first channel layers, and The second transistor above is: Second channel layers spaced apart from each other in the vertical direction above; and It includes a second work function layer on the second channel layers above, and The above second work function layer is an integrated circuit device spaced apart from the first channel layers by the above first work function layer.
12. In Article 11, The above first work function layer is an integrated circuit device in contact with the insulator.
13. In Article 11, The second work function layer includes a second internal work function layer and a second external work function layer, and The second internal work function layer is located between adjacent second channel layers among the second channel layers, and The second external work function layer extends around the second channel layers and the second internal work function layer, and The above second work function layer is an integrated circuit device having an interface between the second internal work function layer and the second external work function layer.
14. In Article 13, The first work function layer includes a first internal work function layer and a first external work function layer, and The first internal work function layer is located between adjacent first channel layers among the first channel layers, and The first external work function layer extends around the first channel layers and the first internal work function layer, and An integrated circuit device in which the first work function layer does not have an interface between the first internal work function layer and the first external work function layer.
15. In Article 14, An integrated circuit device configured such that the first internal work function layer and the first external work function layer form an integrated structure.
16. In Article 11, The above first work function layer comprises a first material, and The above second work function layer is an integrated circuit device comprising a second material different from the first material.
17. A first stack having first channel layers is formed on a substrate, and a second stack having second channel layers is formed on the first stack, wherein the first channel layers are spaced apart from each other in a vertical direction perpendicular to the upper surface of the substrate, and the second channel layers are spaced apart from each other in the vertical direction; Forming an insulator between the first stack and the second stack in the vertical direction; Forming the first channel layers, the second channel layers, and a dummy layer extending around the insulator; Replacing the upper part of the above dummy layer with a first internal work function layer located on the second channel layers; Replacing the lower part of the above dummy layer with a second work function layer located on the first channel layers; and The method comprises forming a first external work function layer located on the first internal work function layer, the insulator, and the second work function layer, wherein A method for manufacturing an integrated circuit device in which the first external work function layer is separated from the first channel layers by the second work function layer.
18. In Article 17, A method for manufacturing an integrated circuit device in which the first external work function layer contacts the first internal work function layer.
19. In Article 18, A method for manufacturing an integrated circuit device comprising an interface between the first internal work function layer and the first external work function layer.
20. In Article 19, The first internal work function layer and the first external work function layer comprise a first material, and A method for manufacturing an integrated circuit device wherein the second work function layer comprises a second material different from the first material.

Description

Integrated circuit device including stacked transistors with matched work function matching scheme and method of manufacturing the same The present disclosure generally relates to an integrated circuit device, and more specifically to an integrated circuit device comprising a stacked transistor. To increase integration density, various structures of integrated circuit devices and methods for manufacturing the same are being proposed. As an example, a stacked transistor structure comprising a plurality of stacked transistors is being proposed. FIG. 1 is a cross-sectional view of an integrated circuit device according to some embodiments. FIG. 2 is a flowchart of a method for manufacturing an integrated circuit device according to some embodiments. FIGS. 3 through 19 are cross-sectional views of a method for manufacturing an integrated circuit device according to some embodiments. FIG. 3 is a cross-sectional view of an intermediate process including forming a gate-to-gate sacrificial layer in a stack. FIG. 4 is a cross-sectional view of an intermediate process including removing a portion of the gate-to-gate sacrificial layer and a portion of the stack. FIGS. 5 and 6 are cross-sectional views of an intermediate process including replacing the gate-to-gate sacrificial layer with an insulator. FIG. 7 is a cross-sectional view of an intermediate process including removing the sacrificial layers. FIG. 8 is a cross-sectional view of an intermediate process including forming a dummy layer. FIG. 9 is a cross-sectional view of an intermediate process including removing an outer dummy layer. FIG. 10 is a cross-sectional view of an intermediate process including forming a first block layer. FIG. 11 is a cross-sectional view of an intermediate process including removing an upper inner dummy layer. FIG. 12 is a cross-sectional view of an intermediate process including removing the first block layer. FIG. 13 is a cross-sectional view of an intermediate process including forming a second pre-work function layer. FIG. 14 is a cross-sectional view of an intermediate process including removing the second external preliminary work function layer. FIG. 15 is a cross-sectional view of an intermediate process including removing lower internal dummy layers. FIG. 16 is a cross-sectional view of an intermediate process including forming a first preliminary work function layer. FIG. 17 is a cross-sectional view of an intermediate process including forming a second block layer. FIG. 18 is a cross-sectional view of an intermediate process including removing a portion of the first preliminary work function layer. FIG. 19 is a cross-sectional view of an intermediate process including removing the second block layer. According to embodiments of the present specification, an integrated circuit device may include a stacked transistor structure comprising a first transistor (e.g., a lower transistor) and a second transistor (e.g., an upper transistor) stacked vertically on a substrate. The first transistor may include first channel layers (e.g., lower channel layers) spaced apart from each other in a vertical direction perpendicular to the upper surface of the substrate. The first transistor may further include a first work function layer (e.g., a lower work function layer) on the first channel layers. The first transistor may further include first gate insulators (e.g., lower gate insulators) between the first work function layer and the first channel layers and a first gate electrode (e.g., a lower gate electrode) on the first work function layer. The second transistor may include second channel layers (e.g., upper channel layers) spaced apart from each other in the vertical direction. The second transistor may further include a second work function layer (e.g., an upper work function layer) on the second channel layers. The second transistor may further include second gate insulators (e.g., upper gate insulators) between the second work function layer and the second channel layers, and a second gate electrode (e.g., an upper gate electrode) on the second work function layer. In some embodiments, each of the first channel layers and each of the second channel layers may be a nanosheet or a nanowire. The integrated circuit device may further include an insulator (also referred to as a gate-to-gate insulator or intermediate dielectric isolation) located between the first transistor (e.g., the first channel layers) and the second transistor (e.g., the second channel layers) in the vertical direction. The first work function layer may include a first inner work function layer and a first outer work function layer. The first internal work function layer may be located between the (adjacent) first channel layers in the vertical direction. The first external work function layer may extend around the first channel layers and the first internal work function layer. The first external work function layer may be located between the insulator and the