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KR-20260067978-A - Semiconductor device and method of manufacturing the same

KR20260067978AKR 20260067978 AKR20260067978 AKR 20260067978AKR-20260067978-A

Abstract

A semiconductor device and a method for manufacturing the same are provided, wherein the semiconductor device comprises a substrate and a semiconductor element located on the substrate, and the semiconductor element comprises a channel structure and a first electrode, a gate electrode, and a second electrode that are spaced apart along a vertical direction and stacked sequentially, wherein the channel structure comprises a channel layer and a gate insulating layer, wherein the channel structure extends along a vertical direction, penetrates the gate electrode, and is connected between the first electrode and the second electrode, and the gate insulating layer is located between the gate electrode and the channel layer. The channel layer of the present application has superior crystal characteristics and can have various shape structures, and the channel layer is no longer limited to an annular shape and can increase the channel area, which helps to improve leakage current and increase operating current, and furthermore can improve the electrical performance of the semiconductor device.

Inventors

  • 왕, 징하오

Assignees

  • 스웨이슈어 테크놀러지 컴퍼니 리미티드

Dates

Publication Date
20260513
Application Date
20250929
Priority Date
20241106

Claims (20)

  1. As a semiconductor device, It includes a substrate and a semiconductor device located on the substrate; The semiconductor device comprises a channel structure and a first electrode, a gate electrode, and a second electrode that are spaced apart along a vertical direction and stacked sequentially, wherein the channel structure comprises a channel layer and a gate insulating layer, wherein the channel structure extends along a vertical direction, penetrates the gate electrode, and is connected between the first electrode and the second electrode, and wherein the gate insulating layer is located between the gate electrode and the channel layer.
  2. In paragraph 1, The semiconductor device further comprises a first insulating layer, wherein the first insulating layer is manufactured as the same layer as the gate insulating layer and extends horizontally between the first electrode and the gate electrode.
  3. In paragraph 2, A semiconductor device characterized in that the first insulating layer is in contact with the first electrode.
  4. In paragraph 2, A semiconductor device characterized in that the first insulating layer is in contact with the gate electrode.
  5. In paragraph 1, A semiconductor device characterized in that the gap between one end connected to the second electrode of the channel layer and the gate electrode is smaller than the gap between one end contacting the second electrode of the gate insulating layer and the gate electrode.
  6. In paragraph 5, The second electrode comprises a first portion in contact with the channel layer and a second portion located on one side of the first portion spaced apart from the channel layer; The semiconductor device further comprises an insulating dielectric layer, wherein the insulating dielectric layer is located between the second portion and the gate electrode, and the orthographic projection of the insulating dielectric layer on the substrate does not overlap with the orthographic projection of the channel structure on the substrate.
  7. In paragraph 1, The semiconductor device further comprises a first signal line, wherein the first signal line is formed integrally with the first electrode and extends along a first horizontal direction, and the orthographic projection of the first electrode on the substrate is located within the orthographic projection of the first signal line on the substrate.
  8. In Paragraph 7, If the orthographic boundary of the channel layer on the substrate exceeds the orthographic projection of the first signal line on the substrate, A semiconductor device characterized in that the orthographic boundary of the channel layer on the substrate overlaps with a portion of the edge of the orthographic projection of the first signal line on the substrate, but does not exceed the orthographic projection of the first signal line on the substrate.
  9. In paragraph 1, A semiconductor device characterized in that the orthographic projection of the above channel structure on the substrate includes an annular shape, and the orthographic projection of the gate electrode on the substrate includes a third portion located within the annular shape and a fourth portion located outside the annular shape.
  10. In paragraph 1, A semiconductor device characterized in that the orthographic projection of the above-described channel structure on the substrate includes a plurality of fifth portions, the gate electrode includes a sixth portion surrounding each of the fifth portions, and the sixth portion within the gate electrode is integrally formed.
  11. In Paragraph 10, The orthographic projection of the above-mentioned fifth part on the substrate is striped and parallel to each other, A semiconductor device characterized by further including a seventh portion in which the projection of the fifth portion on the substrate is annular and the gate electrode is located within the annular portion.
  12. In paragraph 1, The first electrode comprises a first contact material layer and a conductor layer, wherein the first contact material layer is located between the conductor layer and the channel layer, and A semiconductor device characterized in that the second electrode comprises a second contact material layer.
  13. As a method for manufacturing a semiconductor device, Provides a substrate; A first electrode, a channel layer, a gate insulating layer, and a gate electrode are sequentially manufactured on the above substrate; The method includes the step of manufacturing a second electrode on the substrate, A method for manufacturing a semiconductor device characterized in that the channel layer is extended in a vertical direction and connected between the first electrode and the second electrode, and the gate insulating layer is located between the gate electrode and the channel layer.
  14. In Paragraph 13, The manufacture of the above channel layer is, A semiconductor material layer is manufactured on the first electrode; A method for manufacturing a semiconductor device comprising manufacturing a first patterned mask layer on the semiconductor material layer, and etching the semiconductor material layer using the first patterned mask layer as a mask to form the channel layer.
  15. In Paragraph 14, The first patterned mask layer comprises at least one portion, and the orthographic projection of the portion onto the substrate comprises an annular or square shape; and A method for manufacturing a semiconductor device characterized by at least one of the following: the orthographic projection of the first patterned mask layer on a substrate including a plurality of parallel stripe shapes.
  16. In Paragraph 14, Manufacturing the above second electrode is, Before manufacturing the first patterned mask layer, a contact material layer is manufactured on the semiconductor material layer; The method includes etching the semiconductor material layer using the first patterned mask layer as a mask, and simultaneously patterning the contact material layer to form an upper contact portion. A method for manufacturing a semiconductor device characterized in that the second electrode includes the upper contact portion.
  17. In Paragraph 16, The above manufacturing method is, The method further comprises manufacturing a first signal line, wherein the first signal line is manufactured simultaneously with the first electrode, and the orthographic projection of the first electrode on the substrate is located within the orthographic projection of the first signal line on the substrate; Manufacturing the above gate insulating layer and the above gate electrode is, A gate insulating material layer covering the channel layer, the upper contact portion, the first electrode, and the first signal line is manufactured; A gate electrode material layer covering the above gate insulating material layer is manufactured; The gate electrode is formed by patterning and etching the gate electrode material layer, wherein the surface of the gate electrode on one side spaced apart from the substrate is lower than the channel layer; Manufactures the above gate insulating material layer and the insulating dielectric layer covering the above gate electrode; A method for manufacturing a semiconductor device characterized by removing a portion of the insulating dielectric layer and a portion of the gate insulating material layer to expose the upper contact portion, wherein the gate insulating material layer located on one side adjacent to the channel layer of the gate electrode is formed as the gate insulating layer.
  18. In Paragraph 17, A method for manufacturing a semiconductor device, characterized in that manufacturing the second electrode further includes, after exposing the upper contact portion, manufacturing a connection portion at one end spaced apart from the channel layer of the upper contact portion, and the second electrode further includes the connection portion.
  19. In Paragraph 17, In the orthographic projection on the above substrate, The first patterned mask layer includes a ring, and the gate electrode includes a portion located within the ring and a portion located outside the ring, or A method for manufacturing a semiconductor device characterized in that the first patterned mask layer comprises a plurality of portions, and the gate electrode surrounds each of the said portions.
  20. In Paragraph 16, The method further comprises manufacturing a first signal line, wherein the first signal line is manufactured simultaneously with the first electrode, and the orthographic projection of the first electrode on the substrate is located within the orthographic projection of the first signal line on the substrate; A method for manufacturing a semiconductor device characterized in that the orthographic boundary of the first patterned mask layer on the substrate exceeds the orthographic projection of the first signal line on the substrate, or overlaps with the edge portion of the orthographic projection of the first signal line on the substrate but does not exceed the orthographic projection of the first signal line on the substrate.

Description

Semiconductor device and method of manufacturing the same This application relates to the field of semiconductor technology, and more specifically, to a semiconductor device and a method for manufacturing the same. Dynamic Random Access Memory (DRAM) is a type of semiconductor memory that has advantages such as large capacity and low cost, and is widely applied in various fields. The basic memory cell of a standard DRAM is a 1T1C (1 Transistor-1 Capacitor) memory cell, and a 1T1C memory cell requires one transistor and one capacitor. With the advancement of 3D memory processes, vertical channel transistor structures are increasingly being used. In transistors with a vertical channel structure, the switching of the channel layer is controlled by word lines (WL) between wiring layers. However, the channel layer of the related technology is usually limited to a circular shape, and because the channel layer is manufactured after the WL is formed, the crystal characteristics of the channel layer are poor, which further leads to a degradation of the electrical performance of the memory. The following attached drawings of this application are part of this application and are used to help understand this application. The drawings illustrate embodiments of this application and descriptions thereof, and are intended to explain the apparatus and principles of this application. In the drawing: FIGS. 1a to 1n show schematic diagrams of cross-sections along the first and second directions of a device obtained by sequentially performing a method for manufacturing a semiconductor device according to one specific embodiment of the present application. FIGS. 2a to 2g show plan schematic diagrams of a device obtained by sequentially performing a method for manufacturing a semiconductor device according to one specific embodiment of the present application. FIGS. 3a to 3f show schematic orthographic projections of a semiconductor device according to one specific embodiment of the present application. FIG. 4 shows a flowchart of a method for manufacturing a semiconductor device according to one specific embodiment of the present application. Next, embodiments of the present application are described in conjunction with the accompanying drawings to provide a more complete description of the application. However, the present application may be practiced in various forms and should not be interpreted as being limited to the embodiments presented herein. Rather, the provision of such embodiments is intended to make the disclosure of the application thorough and complete and to fully convey the scope of the application to those skilled in the art. In the accompanying drawings, the sizes and relative dimensions of layers and regions may be exaggerated for clarity. Identical reference numerals from beginning to end indicate identical components. It must be understood that when a component or layer is described as "located on," "adjacent to," "connected to," or "combined to," it means that the component or layer may be directly on, adjacent to, connected to, or combined with another component or layer, or that another component or layer may exist between them. On the other hand, when a component is described as "directly located on," "directly adjacent to," "directly connected to," or "directly combined," it means that no component or layer exists between them. Various components, parts, regions, layers, and/or parts may be described using terms such as first, second, third, etc., but it is clear that these components, parts, regions, layers, and/or parts should not be limited by these terms. These terms are used merely to distinguish one component, part, region, layer, or part from another component, part, region, layer, or part. Accordingly, without departing from the teachings of the present application, the first component, part, region, layer, or part discussed below may represent the second component, part, region, layer, or part. Spatial relationship terms, such as “…under,” “…on the underside,” “of the underside,” “below,” “…on top,” etc., may be used herein to conveniently describe the relationship between one component or feature shown in the drawings and another component or feature. In addition to the directions indicated in the drawings, these spatial relationship terms should be understood to include various directions during the use and operation of the device. For example, if the device depicted in the attached drawings is inverted, a component or feature described as “under another component” or “below it” would actually be located “above” the other component or feature. Therefore, the exemplary terms “…under” and “…lower” may include both upward and downward directions. Furthermore, the device may be positioned in different directions (e.g., rotated 90 degrees or other directions), and the spatial descriptions used in this document should be interpreted accordingly. The purpose of the terms used herein is merely to de