KR-20260067988-A - CIRCUIT BOARD AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME

Abstract

An embodiment of the present invention discloses a circuit board comprising: a core layer; a first upper build-up insulating portion including at least one first upper build-up layer stacked along a vertical direction on the core layer; a second upper build-up insulating portion including at least one second upper build-up layer on the first upper build-up insulating portion; a core electrode portion including a core via electrode penetrating the core layer and a core wiring portion disposed on the core layer; a first upper electrode portion including a first via electrode penetrating a first through-hole of the first upper build-up layer and a first wiring portion disposed on the first upper build-up layer; and a second upper electrode portion including a second via electrode penetrating a second through-hole of the second upper build-up layer and a second wiring portion disposed on the second upper build-up layer; wherein the second upper build-up layer includes a second filler having a diameter smaller than that of the first filler of the first upper build-up layer and a second resin, and the roughness of the second filler exposed on the inner wall surface of the second through-hole is different from the roughness of the exposed second resin.

Inventors

• 정순오
• 한영주
• 노진미
• 김학성
• 이세민
• 전나현
• 노현지
• 엄희진

Assignees

• 엘지이노텍 주식회사
• 한양대학교 산학협력단

Dates

Publication Date

20260513

Application Date

20251027

Priority Date

20241106

Claims (10)

1. Core layer; A first upper build-up insulating portion comprising at least one first upper build-up layer stacked along a vertical direction on the core layer; A second upper build-up insulating portion comprising at least one second upper build-up layer on the first upper build-up insulating portion; A core electrode portion comprising a core via electrode penetrating the core layer and a core wiring portion disposed on the core layer; A first upper electrode portion comprising a first via electrode penetrating a first through hole of the first upper build-up layer and a first wiring portion disposed on the first upper build-up layer; and A second upper electrode portion comprising a second via electrode penetrating a second through hole of the second upper build-up layer and a second wiring portion disposed on the second upper build-up layer; The second upper build-up layer comprises a second filler having a diameter smaller than that of the first filler of the first upper build-up layer and a second resin, and A circuit board in which the roughness of the second filler exposed on the inner wall surface of the second through hole is different from the roughness of the exposed second resin.
2. In paragraph 1, A circuit board in which the roughness of the second filler exposed on the inner wall surface of the second through hole is greater than the roughness of the exposed second resin.
3. In paragraph 1, A circuit board in which the roughness on the inner wall surface of the second through hole is smaller than the roughness on the inner wall surface of the first through hole.
4. In paragraph 1, The first upper electrode portion comprises a first seed layer and a first plating layer disposed on the first seed layer, and The above second upper electrode portion is a circuit board comprising a second seed layer and a second plating layer disposed on the second seed layer.
5. In paragraph 4, The above second seed layer is a circuit board having the largest proportion of (002) orientation.
6. In paragraph 4, A circuit board in which the thickness of the first seed layer of the first upper electrode portion is greater than the thickness of the second seed layer of the second upper electrode portion.
7. In paragraph 4, The first seed layer of the first upper electrode portion comprises a 1-1 layer and a 1-2 layer disposed on the 1-1 layer, and A circuit board comprising a second seed layer of the second upper electrode portion, a second-1 layer, and a second-2 layer disposed on the second-1 layer.
8. In Paragraph 7, The above 1-1 layer is a metal layer, and The above 2-1 layer is a circuit board that is a metal alloy layer.
9. In paragraph 8, A circuit board in which the thickness of the above 1-1 layer is greater than the thickness of the above 2-1 layer.
10. In paragraph 1, A circuit board in which the thickness of the first upper build-up layer is greater than the thickness of the second upper build-up layer.

Description

Circuit board and semiconductor package including the same An embodiment according to the present invention relates to a circuit board and a semiconductor package. As the performance of electrical and electronic products advances, technologies are being proposed and researched to attach a larger number of packages to substrates of limited size. However, since conventional packages are based on mounting a single semiconductor chip, there are limitations in achieving the desired performance. Conventional circuit boards or package boards feature a form in which a processor package, housing a processor chip, and a memory package, housing a memory chip, are connected as a single unit. By manufacturing the processor and memory chips into a single integrated package, such package boards offer the advantages of reducing the chip mounting area and enabling high-speed signals through short paths. Due to these benefits, such package boards are widely applied in mobile devices and the like. Meanwhile, recently, due to the high specifications of electronic devices such as servers and PCs, the size of packages is increasing. In addition, as the functions required of processors increase, there is a demand for circuit boards capable of configuring these functions separately as processor chips, mounting these processor chips, and interconnecting the processor chips. Furthermore, regarding the above processor, even when it is separated into two processor chips according to function, the number of terminals (Input/Output) provided on each processor chip is increasing. Recently, due to factors such as 5G, the Internet of Things (IoT), improved image quality, and increased communication speeds, the number of terminals on processor chips is gradually increasing as the number of power and signals grows. Consequently, the area, thickness, and circuit pattern density of circuit boards are also increasing. When the area and thickness of a circuit board increase, it becomes difficult to miniaturize the product, and problems such as increased reliability (e.g., board warping), yield, and product cost arise. Furthermore, to ensure inter-processor chips, miniaturization of circuit patterns is required to align the pitch between the chips and the circuit board. In other words, increasing the density of circuit patterns is more advantageous in terms of product cost, reliability (e.g., warping), and product characteristics than increasing the area and thickness of the circuit board. Therefore, miniaturization of circuit patterns or through-electrodes is required. Furthermore, for package substrates (e.g., interposers) used for HBM or multi-die combination, it is essential to have via holes with fine line widths or pitches and plating on the outermost layer. In this regard, when forming circuit patterns with fine line widths or pitches, the bumps formed on the protective layer covering the fine pattern are also becoming miniaturized in correspondence with the fine pattern. Consequently, due to this miniaturization, the volume of the vias formed on the protective layer is decreasing. Therefore, there is a difficulty in that reliability is reduced due to a decrease in the bonding strength between the bumps and the protective layer. Furthermore, various technical methods are applied in the formation of wiring sections. For via formation, mechanical drilling, laser drilling, chemical etching, and plasma etching are applied. However, mechanical drilling presents a problem in that it is difficult to process micro vias due to the difficulty of fine control. Moreover, chemical etching is also applied restrictively due to the difficulty of controlling etching depth, and it is difficult to apply when both fine patterns and general patterns are used. Consequently, when forming via electrodes for fine control, the plating is not formed uniformly on the inner surface of the via, and the width is significantly reduced, which can lead to a significant decrease in the bonding strength between the via electrode and the insulating layer. As a result, there is a problem in which both the electrical and mechanical reliability of the circuit board are reduced. FIG. 1 is a cross-sectional view of a circuit board according to an embodiment of the present invention, and FIG. 2 is an enlarged view of the K1 portion in FIG. 1, and FIG. 3 is an enlarged view of the K2 portion in FIG. 2, and FIG. 4 is an enlarged view of the K3 portion in FIG. 2, and FIG. 5 is an enlarged view of the K4 portion in FIG. 2, and FIG. 6 is an enlarged view of the K5 portion in FIG. 5, and FIG. 7 is an enlarged view of the K6 portion in FIG. 5, and FIG. 8 is an image of a circuit board according to an embodiment, and FIG. 9 is a graph of the bonding strength, roughness, and electrical conductivity according to the treatment for the second upper build-up layer, and FIG. 10 is a TEM image between the second upper build-up layer and the second seed layer according to the treatment for the sec