KR-20260068010-A - PULSE WIDTH MODULATION SIGNAL GENERATOR AND METHOD

Abstract

A semiconductor device is provided for generating a PWM modulation signal, such as an optimized pulse pattern (OPP). An adc (42) outputs the angle of a motor and is connected to a coprocessor (52), such as a digital signal processor (DSP). The coprocessor (52) has an observer (44) connected to an angle input for generating the motor angle, and a lookup table (48) for generating a PWM signal as a direct function of the generated motor angle. The PWM signal is output to a timer unit (50). A computation unit (46) has an input connected to the coprocessor (52), and the computation unit is configured to select a lookup table based on the generated motor angle and store the selected lookup table as the lookup table (48).

Inventors

• 예프레모프 미하일
• 셰퍼 위르겐
• 트렌틴 알베르토
• 샤이버트 클라우스
• 보이틀랜더 아른트
• 오거스틴 마이클

Assignees

• 인피니언 테크놀로지스 아게

Dates

Publication Date

20260513

Application Date

20251105

Priority Date

20241106

Claims (17)

1. As a semiconductor device for generating a pulse pattern signal, An analog-to-digital converter (ADC) connected to a motor and having an output indicating the angle of the motor, and A coprocessor having an angle input connected to the output of the above ADC, an observer connected to the angle input for determining a motor angle, a coprocessor lookup table for generating a pulse pattern signal as a direct function of the determined motor angle, and a pulse pattern signal output for outputting the pulse pattern signal, and It includes a computational unit having an input connected to the above-mentioned coprocessor, The calculation unit is configured to select a lookup table from a plurality of lookup tables based on determined motor states, such as acceleration and torque, for example, and to store the selected lookup table as a coprocessor lookup table within the coprocessor. Semiconductor device.
2. In paragraph 1, A memory storing the above-mentioned plurality of lookup tables, and A direct memory access (DMA) unit further comprising for directly loading a lookup table selected by the above computation unit into the coprocessor as the coprocessor lookup table, Semiconductor device.
3. In paragraph 1 or 2, The above observer includes a loop output connected to the above computation unit, and also additionally determine the motor speed, and The determined motor speed and the determined motor angle are output to the calculation unit through the loop output, It is configured to output the above angle to the above lookup table, and The calculation unit is configured to select the lookup table based on the determined motor angle and the determined motor speed, Semiconductor device.
4. In any one of paragraphs 1 through 3, The above lookup table is configured to generate the pulse pattern signal at a first speed, and The above calculation unit is configured to select the pulse pattern signal at a second speed, wherein the second speed is at least five times slower than the first speed, Semiconductor device.
5. In any one of paragraphs 1 through 4, The system further includes a timer unit connected to the pulse pattern signal output of the above-mentioned coprocessor, wherein the timer unit An input connected to the pulse pattern signal output of the above coprocessor, and a positive side output and a negative side output for outputting a high side pulse pattern signal and a low side pulse pattern signal for driving a half bridge, Semiconductor device.
6. In paragraph 5, It is intended to drive an inverter for a three-phase motor, wherein the inverter comprises three half-bridges, and the timer unit comprises three output pairs for driving each half-bridge, each output pair comprising a positive output and a negative output. Semiconductor device.
7. In paragraph 5, It includes three parallel lookup tables, each lookup table being intended to generate its own PWM signal as a direct function of the generated motor angle, and Includes three parallel pulse pattern signal outputs for outputting the above pulse pattern signals to respective timer units, Semiconductor device.
8. In paragraph 6 or 7, The above semiconductor device It further includes a sampling time service request link from the above coprocessor to the above timer unit, and The above coprocessor is configured to generate a plurality of pulse pattern signals, sequentially output the plurality of pulse pattern signals at the pulse pattern signal output, and output a signal on the sampling time service request link to signal the timer unit when a pulse pattern output signal exists at the pulse pattern signal output. Semiconductor device.
9. In paragraph 8, The above timer unit is, A sampling unit having an input connected to the pulse pattern output of the above coprocessor, and sampling the pulse pattern signal on the pulse pattern signal output when indicated in the sampling time service request link, and A dead time and inversion unit comprising a sampling input connected to the output of the above-mentioned sampling unit, and further comprising a positive-side output unit and a negative-side output unit for each output pair, wherein the dead time and inversion unit is configured to generate the high-side pulse pattern signal and the low-side pulse pattern signal, respectively, at the positive-side output unit and the negative-side output unit from a signal on the above-mentioned sampling signal input. Semiconductor device.
10. In Article 8 or 9, A synchronization service request link from the ADC to the timer unit for signaling the existence of new digitized data captured by the ADC, further comprising Semiconductor device.
11. As a system, A semiconductor device according to any one of paragraphs 1 through 10, and A semiconductor device comprising at least one half-bridge, each including a high-side transistor connected to the positive-side output of the semiconductor device and a low-side transistor connected to the low-side output of the semiconductor device. System.
12. As a method for generating a pulse pattern signal, A step of digitizing a signal representing the angle of the motor, and A step of determining a motor angle from the digitized signal using an observer, and A step of generating a pulse pattern signal as a direct function of the generated motor angle using a lookup table, and outputting the pulse pattern signal; For example, including the step of selecting a lookup table in a calculation unit based on a determined motor state, such as acceleration and torque, and storing the selected lookup table as a lookup table. method.
13. In Paragraph 12, A method further comprising the step of generating a motor speed using the above observer and outputting the motor speed to the above calculation unit. method.
14. In Article 12 or Article 13, The method further comprises the step of generating a high-side signal and a low-side signal for driving a half-bridge from the pulse pattern signal, and driving the half-bridge with the high-side signal and the low-side signal. method.
15. In any one of paragraphs 12 through 14, To drive an inverter for a three-phase motor having three half-bridges, the method A method comprising the step of generating three distinct pulse pattern signals as a direct function of a generated motor angle using three lookup tables, and outputting said pulse pattern signals. method.
16. In paragraph 15, A method further comprising the step of sequentially outputting a plurality of PWM signals in a pulse pattern signal output, and outputting a signal on a sampling time service request link to signal when a pulse pattern output signal exists in the pulse pattern signal output. method.
17. In any one of paragraphs 12 through 16, The step of generating the above pulse pattern signal at a first speed, and The step of selecting the pulse pattern signal at a second speed that is at least five times slower than the first speed, method.

Description

Pulse Width Modulation Signal Generator and Method The present invention relates to a method for generating a pulse width modulation signal and, in particular, to a semiconductor device for generating a signal used for motor driving. It is necessary to drive electric motors efficiently. For example, in the powertrain of an electric or hybrid vehicle, the electric motor is driven from the battery by multiple drivers. Typically, six power transistors arranged in three half-bridges are used to drive a three-phase electric motor. Power transistors are driven by a signal, typically a pulse width modulation signal, meaning they operate in an on or off state. Power transistors are driven by a driver controlled by a control device (e.g., a microcontroller) that generates the signal. One known approach is Space Vector Pulse Width Modulation (PWM). When using this approach, it is possible to generate a PWM signal in which ripple and harmonic distortion are reduced as the switching frequency increases, which enables the reduction of losses in the motor. An approach to prevent excessive losses in motors is generally required. According to the first embodiment, as a semiconductor device for generating a pulse pattern signal, An analog-to-digital converter (ADC) connected to a motor and having an output indicating the angle of the motor, and A coprocessor having an angle input connected to the output of an ADC, an observer connected to the angle input for determining a motor angle, a coprocessor lookup table for generating a PWM pulse pattern signal as a direct function of the determined motor angle, and a pulse pattern signal output for outputting a pulse pattern signal, and A semiconductor device is provided, comprising a computational unit having an input connected to the above-mentioned coprocessor, wherein the computational unit is configured to select a lookup table from a plurality of lookup tables based on a determined motor state, such as acceleration and torque, and to store the selected lookup table as a coprocessor lookup table within the coprocessor. By using a lookup table within the coprocessor, this example provides a first loop driven directly from an angle measurement, which can provide a high-speed loop without requiring a complex structure within the semiconductor device. By directly generating a pulse pattern signal from the output of an analog-to-digital converter (ADC), the pulse pattern signal can be provided as quickly as the ADC can provide the signal. Thus, the ADC and DSP provide a high-speed loop, and the update of the lookup table by the compute unit constitutes a second, slower outer loop. For example, the high-speed loop can operate in a time range of less than 10 μs, for example, less than 2 μs, and the outer loop containing the compute unit can operate in a time range of more than 20 μs, for example, more than 40 μs. This ultimately allows computation to be performed in the outer loop using a conventional microcontroller general-purpose core, and other embodiments may use other hardware, such as other cores within a parallel processing unit. Now, with reference to the attached drawings, embodiments of the present invention will be described merely as examples. Figure 1 illustrates an optimized pulse pattern (A) and a regular pulse pattern (B). Figure 2 illustrates a driving signal for a driver together with a driver. Figure 3 illustrates an exemplary configuration. Figure 4 illustrates an additional exemplary configuration. Figure 5 illustrates a PWM signal. Figure 6 illustrates the driving signal. Figure 7 illustrates an additional exemplary configuration. Figure 8 illustrates a signal corresponding to the configuration of Figure 7. Embodiments of the present invention are presented purely by example. FIG. 1 illustrates an example of an optimized pulse pattern (A) and a conventional regular pulse pattern (B) used for motor driving. The regular pulse pattern (B) starts pulses at regular intervals and adjusts the length of the pulses to provide pulse width modulation (PWM). Optimized pulse patterns (OPP) can be used to provide signals with lower total harmonic distortion (THD) than spatial vector pulse width modulation. In these optimized patterns, switching is not limited to constant intervals but occurs at selected times to reduce THD and loss. For example, an OPP using a switching frequency of 9 kHz can deliver a THD of 2.3%. On the other hand, an SVPWM method using the same 9 kHz switching frequency can deliver a current signal with a THD of 5.7%. To achieve a similar THD of 2.35%, the switching frequency must be increased to 20 kHz. Such a high switching frequency means that the half-bridge transistors driving the motor switch more frequently, leading to increased switching losses. Therefore, using an OPP can significantly increase efficiency and reduce losses, which leads to reduced heat generation and makes it easier to maintain the semiconductor and motor within a temperature rang