KR-20260068019-A - Die-to-die input/output signal routing using opposing die surfaces in integrated circuit component packaging

Abstract

Input/output (I/O) routing from one integrated circuit die to another in an integrated circuit component comprising heterogeneous and vertically stacked dies is performed from the upper and lower surfaces of the integrated circuit dies to the other dies. Die-to-die I/O routing from a die to a laterally adjacent die is performed from the upper surface of the die through one or more redistribution layers. Die-to-die routing from a die to a vertically adjacent die is performed through hybrid bonding on the lower surface of the die. Embedded bridges or chiplets are not used for die-to-die I/O routing, which allows space for more through-dielectric vias to provide power and ground connections to the dies and can provide improved power transfer.

Inventors

• 마지, 프라샨트
• 데슈판데, 니틴 에이.
• 카르하데, 옴카르 쥐.
• 카레, 수르후드 브이.

Assignees

• 인텔 코포레이션

Dates

Publication Date

20260513

Application Date

20240703

Priority Date

20230929

Claims (20)

1. As a device, A first integrated circuit die comprising a first transistor region, a first layer comprising a metal, and a second layer comprising a metal—the first transistor region is located between the first layer and the second layer; a first surface of the first integrated circuit die faces a second surface of the first integrated circuit die, and the first surface of the first integrated circuit die includes a first conductive contact—; A second integrated circuit die positioned laterally with respect to the first integrated circuit die - the second integrated circuit die comprises a second transistor region, a third layer comprising metal, and a fourth layer comprising metal, wherein the second transistor region is positioned between the third layer and the fourth layer, the first surface of the second integrated circuit die faces the second surface of the second integrated circuit die, and the first transistor region and the second transistor region each comprise a plurality of transistors -; A redistribution layer region located on the first surface of the first integrated circuit die and the first surface of the second integrated circuit die - the redistribution layer region includes a fifth layer comprising a metal and a dielectric layer -; and A third integrated circuit die that overlaps at least partially vertically with the first integrated circuit die. A device comprising, wherein the first surface of the third integrated circuit die comprises a second conductive contact attached to the first conductive contact.
2. In claim 1, the device is an integrated circuit component, and the volume extending from the first surface of the first integrated circuit die and the first surface of the second integrated circuit die toward the outer surface of the integrated circuit component in a direction away from the first transistor region does not include an embedded bridge.
3. A device according to claim 1, wherein the redistribution layer region does not include an embedded bridge.
4. A device according to claim 1, wherein the redistribution layer region does not include an embedded structure including metal lines.
5. An apparatus according to any one of claims 1 to 4, wherein the third integrated circuit die and the first integrated circuit die are instances of different integrated circuit die designs.
6. An apparatus according to any one of claims 1 to 5, wherein the third integrated circuit die comprises a silicon through-via extending from the first surface of the third integrated circuit die through at least a portion of the third integrated circuit die.
7. An apparatus according to any one of claims 1 to 6, further comprising a fourth integrated circuit die positioned laterally with respect to the third integrated circuit die and overlapping at least partially perpendicularly with respect to the second integrated circuit die, wherein the first surface of the fourth integrated circuit die comprises a third conductive contact attached to a fourth conductive contact positioned on the second surface of the second integrated circuit die.
8. In Paragraph 7, A dielectric region located between the third integrated circuit die and the fourth integrated circuit die; and A dielectric penetrating via extending through the above dielectric region A device further comprising, wherein the dielectric penetration via is attached to a fifth conductive contact located on the second surface of the first integrated circuit die.
9. In paragraph 8, the above-mentioned genome region is a first genome region, and the device is: A second dielectric region located between the first integrated circuit die and the second integrated circuit die; and A second dielectric through-via extending through the second dielectric region and attached to the first dielectric through-via. A device that further includes
10. A device according to claim 7, further comprising a dielectric region located between the third integrated circuit die and the fourth integrated circuit die, wherein the dielectric region does not include an embedded bridge.
11. A device according to claim 7, further comprising a dielectric region located between the third integrated circuit die and the fourth integrated circuit die, wherein the dielectric region does not include an embedded structure comprising metal lines.
12. A device according to any one of claims 1 to 11, wherein the device comprises an integrated circuit component including the first integrated circuit die, the second integrated circuit die, the third integrated circuit die, and the redistribution layer region.
13. In paragraph 12, the device further comprises a printed circuit board, and the integrated circuit component is attached to the printed circuit board.
14. A device according to claim 13, further comprising one or more second integrated circuit components attached to the printed circuit board.
15. As a method, A step of attaching a first integrated circuit die to the surface of a carrier wafer - the first integrated circuit die comprises a first transistor region, a first layer comprising a metal, and a second layer comprising a metal, wherein the first transistor region is located between the first layer and the second layer -; A step of attaching a second integrated circuit die to the surface of the carrier wafer - the second integrated circuit die comprises a second transistor region, a third layer including a metal, and a fourth layer including a metal, wherein the second transistor region is located between the third layer and the fourth layer -; A step of forming a dielectric layer on the surface of the carrier wafer - the region of the dielectric layer is located between the first integrated circuit die and the second integrated circuit die -; A step of forming a redistribution layer region on the region of the first integrated circuit die, the second integrated circuit die, and the dielectric layer; A step of attaching a substrate to the above redistribution layer region; A step of separating the carrier wafer from the first integrated circuit die, the second integrated circuit die, and the region of the dielectric layer; and A step of attaching a structure to the first integrated circuit die, the region of the dielectric layer, and the second integrated circuit die. A method comprising, wherein the structure comprises a third integrated circuit die, and the step of attaching the structure comprises the step of attaching a portion of the third integrated circuit die to at least a portion of the first integrated circuit die.
16. In paragraph 15, the above redistribution layer region does not include an embedded bridge, method.
17. In paragraph 15, the method wherein the redistribution layer region does not include an embedded structure including metal lines.
18. In claim 15, the structure further comprises a fourth integrated circuit die, and the step of attaching the structure to the first integrated circuit die, the second integrated circuit die and the region of the dielectric layer comprises the step of attaching the fourth integrated circuit die to at least a portion of the second integrated circuit die, the region of the dielectric layer is a first dielectric region, and the structure further comprises a second dielectric region located between the first integrated circuit die and the second integrated circuit die, and further comprises a second dielectric region located between the third integrated circuit die and the fourth integrated circuit die, wherein the second dielectric region does not include an embedded bridge.
19. In claim 15, the structure further comprises a fourth integrated circuit die, and attaching the structure to the first integrated circuit die, the second integrated circuit die and the region of the dielectric layer comprises the step of attaching the fourth integrated circuit die to at least a portion of the second integrated circuit die, wherein the region of the dielectric layer is a first dielectric region, and the structure further comprises a second dielectric region located between the first integrated circuit die and the second integrated circuit die, and further comprises a second dielectric region located between the third integrated circuit die and the fourth integrated circuit die, wherein the second dielectric region does not comprise an embedded structure including metal lines.
20. As a device, First integrated circuit die - The first integrated circuit die is: First transistor; The first surface of the first integrated circuit die; and A second surface of the first integrated circuit die facing the first surface of the first integrated circuit die. ...including, wherein the first surface of the first integrated circuit die includes a first conductive contact, and the second surface of the first integrated circuit die includes a second conductive contact. A second integrated circuit die positioned laterally with respect to the first integrated circuit die - the second integrated circuit die is: Second transistor; The first surface of the second integrated circuit die; and A second surface of the second integrated circuit die facing the first surface of the second integrated circuit die. ...including, wherein the first surface of the second integrated circuit die includes a third conductive contact, and the first surface of the first integrated circuit die and the first surface of the second integrated circuit die are substantially on the same plane -; A first layer comprising a metal - said first layer is conductively bonded to said first conductive contact -; A second layer comprising a metal - said second layer is conductively bonded to said second conductive contact -; and A third integrated circuit die positioned vertically with respect to the first integrated circuit die. A device comprising, wherein the surface of the third integrated circuit die comprises a fourth conductive contact attached to the second conductive contact.

Description

Die-to-die input/output signal routing using opposing die surfaces in integrated circuit component packaging Cross-reference regarding related applications This application claims the benefit and priority of U.S. Patent Application Serial No. 18/478,950, filed September 29, 2024, under the title of the invention “DIE-TO-DIE INPUT/OUTPUT SIGNAL ROUTING UTILIZING OPPOSING DIE SURFACES IN INTEGRATED CIRCUIT COMPONENT PACKAGING”. The disclosure of the prior application is considered part of the disclosure of this application and is accordingly incorporated by reference into the disclosure of this application in its entirety. Integrated circuit components may include heterogeneous integrated circuit dies—dies manufactured of different types (processors, memories, etc.), designs, sizes, and different processing nodes. Die-to-die routing of input/output signals between integrated circuit dies and routing of power signals to integrated circuit dies in an integrated circuit component may include redistribution layers, embedded bridges or chiplets, and dielectric through-vias. Figure 1 is a cross-sectional view of a microelectronic structure using a bridge built in for routing between dies. FIG. 2a is a cross-sectional view of an exemplary microelectronic structure including two integrated circuit dies attached to a carrier wafer. FIG. 2b is a cross-sectional view of the exemplary microelectronic structure of FIG. 2a after removal of the substrate regions of the integrated circuit dies. FIG. 2c is a cross-sectional view of the exemplary microelectronic structure of FIG. 2b after the formation of a liner layer and a dielectric layer on the structure. FIG. 2d is a cross-sectional view of the exemplary microelectronic structure of FIG. 2c after thinning of the dielectric layer and flattening of the resulting top surface of the structure. FIG. 2e is a cross-sectional view of the exemplary microelectronic structure of FIG. 2d after the formation of the redistribution layer region and dielectric through-vias. FIG. 2f is a cross-sectional view of the exemplary microelectronic structure of FIG. 2e after the attachment of a thermomechanical substrate to the structure. FIG. 2g is a cross-sectional view of an exemplary structure of FIG. 2f after the removal of the carrier wafer and the attachment of a bonding layer to a structure including integrated circuit dies. FIG. 3 is an exemplary method for forming a structure including die-to-die routing using the opposing surfaces of an integrated circuit die. FIG. 4 is a plan view of wafers and dies that may be included in a microelectronic assembly according to any of the embodiments disclosed in this specification. FIG. 5 is a cross-sectional side view of an integrated circuit device that may be included in a microelectronic assembly according to any of the embodiments disclosed in this specification. FIGS. 6a-6d are perspective views of exemplary planar, FinFET, gate-all-around, and stacked gate-all-around transistors. FIGS. 7a and 7b are a perspective view and a cross-sectional view of exemplary forksheet gate-all-around transistors. FIGS. 8a and 8b are a perspective view and a cross-sectional view of an exemplary complementary field-effect transistor (CFET) architecture. FIG. 9 is a cross-sectional side view of an integrated circuit device assembly that may include a microelectronic assembly according to any of the embodiments disclosed in this specification. FIG. 10 is a block diagram of an exemplary electrical device that may include a microelectronic assembly according to any of the embodiments disclosed in this specification. The number of cores and caches integrated into integrated circuit components continues to scale across subsequent generations of semiconductor manufacturing technology. Design factors, such as increasing cache-to-core ratios, also contribute to the increase in the number of caches within integrated circuit components. To mitigate the yield impact of integrating more cores and caches onto a single die, core and cache functionalities are being disaggregated into smaller, distinct dies or chiplets. Further driving this disaggregation is the fact that different process nodes may be required for different components within an integrated circuit (e.g., cores, caches, fabric) due to cost, performance, or other reasons. Vertical stacking of chiplets within an integrated circuit component (commonly referred to as "3D packaging") is one approach to reduce the impact of routing I/O signals between dies on performance. As the level of disaggregation increases, the complexity of routing I/O signals between dies increases to meet performance requirements. As the complexity of I/O signal routing between dies increases, the number of interconnect routing layers used to implement die-to-die routing may also increase. FIG. 1 is a cross-sectional view of a microelectronic structure using an embedded bridge for routing between dies. The structure (100) includes two core die