KR-20260068041-A - Quantum Computing Device Featuring Spatially Separated Nuclear Spin-Based Quantum Memory via Deterministic Single-Ion Implantation

KR20260068041AKR 20260068041 AKR20260068041 AKR 20260068041AKR-20260068041-A

Abstract

The present invention relates to a quantum computing device having a spatially separated dual-layer quantum memory architecture that utilizes a single electron spin of a quantum dot formed within an isotope-purified 28 Si semiconductor substrate as a logic qubit, and utilizes a single nucleus spin of a single ³¹P impurity atom disposed at a distance of 10 nm to 20 nm from the outer boundary of the quantum well region by a deterministic single-ion implantation process as a memory qubit. In quantum operation mode, the logic qubit and the memory qubit are completely electrically and magnetically decoupled to suppress mutual decoupling, and in storage mode, the quantum state of the electron is transferred to the nucleus at high speed and high fidelity by a resonance SWAP gate through a dual pulse sequence of ESR pulses and NMR pulses, and is preserved for several seconds or more. A 3D stacked analog CIM NPU generates a SWAP trigger immediately without ADC delay to prevent the collapse of the operation result, and can be expanded into a large-scale quantum random access memory (QRAM) by means of a 2D quantum dot array and a crossbar addressing structure.

Inventors

안범주

Assignees

안범주

Dates

Publication Date: 20260513
Application Date: 20260426

Claims (15)

In a quantum computing device having a quantum memory architecture that performs quantum computation and quantum state storage within a semiconductor substrate, A plurality of quantum dots including a quantum well region in which a single electron is bound to a ground state are formed within the semiconductor substrate, and a logic qubit region that performs high-speed quantum operations using the spin state of the single electron; A memory qubit region formed by a single impurity atom being embedded within the semiconductor substrate at a predetermined distance from the outer boundary of the quantum well region by a deterministic single ion implantation process, and which preserves a quantum state for a long period using the spin state of the nucleus of the impurity atom; and A memory control unit that applies an electromagnetic wave pulse of a specific frequency, mediated by a hyperfine interaction between a specific electron in the logic qubit region and the atomic nucleus in the memory qubit region, to transfer the quantum state of the electron to the atomic nucleus or restore the quantum state of the atomic nucleus to the electron; wherein A quantum computing device equipped with a nuclear spin-based quantum memory, characterized in that the impurity atomic nucleus of the memory qubit region is positioned at a location where substantial hyperfine coupling with the electron wave function does not occur in the quantum operation mode and is electrically and magnetically decoupled from the logic qubit region.
In paragraph 1, The semiconductor substrate is an isotope-purified silicon substrate, and the single impurity atom forming the memory qubit region is a phosphorus atom, A quantum computing device characterized in that the quantum state of the electron is mapped to the nuclear spin state of the phosphorus atom, which has high resistance to ambient noise, and the quantum state is preserved without decay for a period longer than the spin decoherence time of the electron.
In paragraph 1, The above memory control unit is included within an analog computing-in-memory based neural network processing device that is three-dimensionally stacked on top of the semiconductor substrate, and A quantum computing device characterized by the neural network processing device generating a trigger signal for the electromagnetic wave pulse without delay due to digital conversion immediately after the quantum operation cycle of the logic qubit ends, thereby controlling the quantum state, which is the result of the operation, to be immediately stored in the memory qubit area before it collapses due to environmental noise.
In paragraph 1, A quantum computing device characterized by the above-mentioned predetermined separation distance being 10 nanometers or more and 20 nanometers or less.
In paragraph 1, A quantum computing device characterized in that the memory control unit activates the hyperfine interaction by applying a control voltage to a gate electrode formed on the semiconductor substrate in storage mode to extend the wave function of the electron outside the quantum well region and reach the location of the impurity atomic nucleus.
In paragraph 1, A quantum computing device characterized in that the above electromagnetic wave pulse is composed of a dual pulse sequence that sequentially applies an electron spin resonance pulse resonating with the spin transition frequency of the electron and a nuclear magnetic resonance pulse resonating with the spin transition frequency of the atomic nucleus, such that a transition of the quantum state is performed in an eigenmode of the superfine interaction Hamiltonian between the electron and the atomic nucleus.
In paragraph 1, The above impurity atoms are embedded within the bulk region of the semiconductor substrate, spaced apart by a predetermined depth in a vertical direction from the lower boundary surface of the quantum well region, and A quantum computing device characterized in that the wave function of the electron above suppresses expansion in the vertical direction in the operation mode, so that the overlap integral with the impurity atomic nucleus substantially converges to zero.
In paragraph 1, The above memory qubit region forms a multilayer memory structure in which a plurality of impurity atomic nuclei are spaced apart at different distances within the semiconductor substrate, corresponding to a single logic qubit region. A quantum computing device characterized by the above memory control unit selectively designating one of the plurality of impurity atomic nuclei to transition the quantum state of the electron, thereby sequentially backing up the quantum state of a single logic qubit to a plurality of memory qubits.
In paragraph 1, The memory control unit further includes a single-electron transistor formed on the semiconductor substrate adjacent to the memory qubit region, and A quantum computing device characterized by the single-electron transistor non-destructively reading a quantum state stored in an atomic nucleus by detecting a spin-dependent tunneling current of the electron that changes according to the spin state of the impurity atomic nucleus.
In paragraph 1, The memory qubit region comprises: a short-term memory qubit composed of a first impurity nucleus having a decoherence time of a microsecond to millisecond level, positioned close to the quantum well region; and a long-term memory qubit composed of a second impurity nucleus having a decoherence time of a second level or more, positioned further away from the quantum well region than the first impurity nucleus. A quantum computing device characterized in that the memory control unit selectively activates the short-term memory qubit or the long-term memory qubit according to the requirements of the storage period.
In paragraph 1, The above quantum well region is a heterojunction quantum well composed of a silicon-germanium barrier layer and an isotope-purified silicon channel layer, and A quantum computing device characterized in that the impurity atoms do not penetrate the silicon-germanium barrier layer but are embedded within the silicon-germanium barrier layer from the lower boundary surface of the silicon channel layer, and the band offset of the heterojunction physically assists decoupling in the computation mode.
In paragraph 1, The above logic qubit region includes first, second, and third quantum dots arranged adjacent to each other, and A quantum computing device characterized in that the memory control unit encodes the quantum state of an electron bound to each of the first, second, and third quantum dots into a 3-qubit bit-inversion repeat code, and then transfers the quantum state of each encoded physical qubit to the atomic nucleus of the corresponding memory qubit region, so as not to propagate an error of a single physical qubit to the stored quantum state.
In paragraph 1, The above semiconductor substrate is mounted in a dilution refrigerator and maintained at an operating temperature of 50 millikelvin or less, and A quantum computing device characterized in that the memory control unit includes a temperature interlock function that allows the application of the electromagnetic wave pulse only when it is determined that the spin relaxation rate due to thermal excitation at the operating temperature satisfies the condition that it is sufficiently slower than the decoherence time of the atomic nucleus.
In paragraph 1, The memory control unit performs a storage confirmation operation to verify whether the transition is completed by reading the spin state of the electron after transitioning the quantum state of the electron to the atomic nucleus and comparing it with the state prior to the transition. A quantum computing device characterized by executing a feedback loop that reapplies the electromagnetic wave pulse to retry the transition operation when the above verification result is below a preset fidelity threshold.
In paragraph 1, The above logic qubit region forms an array composed of a plurality of quantum dots arranged in a two-dimensional manner in the row and column directions, and The memory qubit region comprises a plurality of impurity atomic nuclei independently arranged corresponding to each of the plurality of quantum dots, wherein A quantum computing device characterized in that the memory control unit selectively performs a transition operation by addressing any one of the plurality of impurity atomic nuclei by a combination of a row selection signal and a column selection signal, thereby causing the entire two-dimensional array to operate as a quantum random access memory.

Description

Quantum Computing Device Featuring Spatially Separated Nuclear Spin-Based Quantum Memory via Deterministic Single-Ion Implantation The present invention relates to a semiconductor-based quantum computing device, and more specifically, to a quantum computing device equipped with a nuclear spin-based quantum random access memory ( QRAM ) that utilizes a single electron spin of a quantum dot formed within an isotope-purified silicon (28 Si) substrate as a logic qubit, and utilizes a nuclear spin of an impurity atom spatially spaced outside the quantum well region of the quantum dot by a deterministic single ion implantation process as a memory qubit, thereby performing quantum state transitions (swap) and restorations (reverse swap) based on electromagnetic wave pulses mediated by hyperfine interactions. Quantum computing is a next-generation information processing paradigm that utilizes quantum mechanical phenomena, represented by superposition and entanglement, as the fundamental principles of information processing, thereby providing computational power that exponentially surpasses classical computing in specific computational domains such as prime factorization, quantum simulation, and optimization problems. In the physical implementation of quantum computing, the computational accuracy of quantum bits, or qubits, and the quantum state preservation time (decoherence time) are the two most critical requirements for the realization of practical quantum computers. Among semiconductor-based quantum computing platforms, the method of utilizing the spin state of a single electron confined to a silicon quantum dot as a qubit possesses outstanding advantages, such as high compatibility with mature manufacturing technologies in the semiconductor industry, high integration potential, and convenience of electrical control. In particular, the isotope-purified 28 Si substrate consists only of nuclides without nuclear spin, and by fundamentally eliminating nuclear spin bath noise caused by 29 Si, a nuclear spin-possessing isotope that accounts for about 4.7% of natural silicon substrates, the decoherence time of electron spin qubits can be significantly extended to the level of several milliseconds (ms) to several hundred milliseconds. However, there is a physical limitation in that the decoherence time of electron spins is fundamentally shorter than that of nuclear spins. The nuclear spin of a phosphorus (³¹P) donor atom in silicon has a decoherence time of several seconds to tens of seconds in an isotope-purified 28 Si substrate, which is several orders of magnitude longer than the decoherence time of electron spins. Due to these characteristics, nuclear spins have long been considered an ideal physical medium for the long-term storage of quantum information. The silicon-based nuclear spin quantum computer architecture (Kane model) proposed by Kane in 1998 suggested a method of encoding information into the nuclear spin of a ³¹P donor atom and performing logical operations and readings using external electric and electromagnetic fields mediated by electrons bound to the donor. However, the Kane model is a structure in which electrons are directly bound to the donor atom, and it contains a fundamental structural dilemma in which it is difficult to simultaneously optimize the two requirements of fast electron spin control for computation and long nuclear spin conservation for storage within a single physical system. Subsequently proposed quantum dot and donor coupling architectures (e.g., US8816325B2) introduced the concept of separating gate-defined quantum dots into operational qubits and the nuclear spins of donor atoms into memory qubits; however, the prior art applies an adiabatic quantum state transition that quasi-statically changes the ultrafine coupling strength between the electron wave function and the donor nucleus through the modulation of the direct current (DC) voltage applied to the A-gate, and does not disclose a specific spatial separation configuration between the quantum well region of the quantum dot and the donor nucleus, nor does it disclose an active decoupling structure in the operational mode resulting therefrom. Furthermore, it does not disclose the precise placement of a single donor nucleus by a deterministic single-ion implantation process, nor does it disclose an electromagnetic pulse-based resonance SWAP gate control method. Therefore, there has been a continuous demand for a new quantum memory architecture that completely separates and optimizes the high-speed computational capabilities of electron spin-based logic qubits and the long-term quantum state preservation capabilities of nuclear spin-based memory qubits based on a physical spatial separation structure, and organically connects the two layers through high-speed resonant swap control using electromagnetic pulses. FIG. 1 is a system block diagram showing the overall configuration of a quantum computing device according to one emb