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KR-20260068045-A - Single-Chip Optical Communication Controller Integrating a CXL Port-Based Silicon Photonics Engine and a Thermal Feedback-Based Intelligent Bandwidth Management System

KR20260068045AKR 20260068045 AKR20260068045 AKR 20260068045AKR-20260068045-A

Abstract

The present invention relates to a single-chip structure CXL-optical communication integrated controller chipset (100) integrated on a silicon substrate (110). The chipset (100) includes a plurality of CXL ports (120) that receive electrical data signals, a silicon photonics engine (130) that converts the data into WDM optical signals, and an intelligent bandwidth management unit (140) that detects heat generated during optical conversion by the silicon photonics engine (130) in real time and dynamically adjusts the transmission bandwidth of the CXL ports (120). The intelligent bandwidth management unit (140) includes a temperature sensor (141) placed adjacent to a ring resonator modulator (131), a lookup table (142), BW control logic (143), a surplus BW reallocation module (144), a wavelength monitoring circuit (145), a thermal prediction model (146), and an isolation policy module (147), thereby providing post-response and preemptive thermal control, wavelength shift self-correction feedback, channel merging adaptive control, and security domain isolation functions.

Inventors

  • 안범주

Assignees

  • 안범주

Dates

Publication Date
20260513
Application Date
20260426

Claims (13)

  1. As a single-chip structure integrated on a silicon substrate, Multiple CXL ports for receiving electrical data signals; A silicon photonics engine for converting data input through the above CXL port into an optical wavelength division multiplexing (WDM) signal; and A CXL-optical communication integrated controller chipset comprising an intelligent bandwidth management unit positioned adjacent to the silicon photonics engine and dynamically adjusting the data transmission bandwidth of the CXL port based on the heat generated during the optical conversion.
  2. In paragraph 1, The above silicon photonics engine is, It includes a plurality of ring resonator modulators, each having a different center wavelength, and A CXL-optical communication integrated controller chipset in which the plurality of ring resonator modulators are coupled in parallel to a single bus waveguide to generate the WDM signal.
  3. In paragraph 2, The above intelligent bandwidth management unit is, Individual temperature measurements are received from a plurality of temperature sensors arranged adjacent to each of the plurality of ring resonator modulators, and A CXL-optical integrated controller chipset that selectively reduces the transmission bandwidth of a CXL port supplying data to a corresponding ring resonator modulator and WDM channel when any of the above individual temperature measurements exceed a preset threshold temperature.
  4. In paragraph 1, The above silicon photonics engine is, It further includes a single integrated III-V semiconductor-based multiwavelength laser light source on the silicon substrate, and The above multiwavelength laser light source is a CXL-optical communication integrated controller chipset that supplies a plurality of carrier wavelengths required for the WDM conversion.
  5. In paragraph 1, A CXL-optical integrated controller chipset, wherein each of the plurality of CXL ports supports a protocol version of CXL 2.0 or higher and includes protocol negotiation logic that selectively enables CXL.io, CXL.cache, and CXL.memory subprotocols.
  6. In paragraph 5, The above plurality of CXL ports support a CXL 3.0-based Multi-Logical Device (MLD) mode, and The above intelligent bandwidth management unit is a CXL-optical communication integrated controller chipset that independently adjusts the bandwidth allocation ratio at the MLD logic device level.
  7. In paragraph 1, The above intelligent bandwidth management unit is, It includes a look-up table that maps a plurality of bandwidth levels corresponding to the measurement temperature of the silicon photonics engine and a plurality of predefined temperature ranges, respectively. A CXL-optical communication integrated controller chipset that gradually reduces the bandwidth of the CXL port according to the temperature range to which the measured temperature belongs.
  8. In paragraph 1, The above intelligent bandwidth management unit is, For the above plurality of CXL ports, independent bandwidth adjustment is performed for each port, and A CXL-optical integrated controller chipset that dynamically reallocates surplus bandwidth capacity resulting from a reduction in bandwidth of a specific CXL port to another CXL port that does not share the same WDM channel as the specific CXL port.
  9. In paragraph 1, It further includes a thermoelectric cooler (TEC) disposed at the bottom of the silicon photonics engine to absorb heat from the silicon substrate, and The above intelligent bandwidth management unit initiates a bandwidth reduction of the CXL port only when the cooling capacity of the thermoelectric element reaches a saturation state, in a CXL-optical communication integrated controller chipset.
  10. In paragraph 1, The above intelligent bandwidth management unit is, It includes a heat prediction model that estimates the amount of heat generated within a predetermined prediction window by monitoring the instantaneous transmission rate of data traffic flowing in through the plurality of CXL ports in real time, and A CXL-optical integrated controller chipset that suppresses the temperature rise of the silicon photonics engine by preemptively reducing the transmission bandwidth of the CXL port before the estimated heat generation amount reaches a threshold.
  11. In paragraph 2, The above intelligent bandwidth management unit is, It further includes a wavelength monitoring circuit that monitors the wavelength detuning between the resonant wavelength of each of the plurality of ring resonator modulators and the target WDM channel wavelength, and A CXL-optical communication integrated controller chipset that, when the wavelength shift exceeds a preset allowable range, reduces the transmission bandwidth of the CXL port corresponding to the ring resonator modulator in proportion to the magnitude of the wavelength shift to lower the modulation power, thereby reducing heat generation of the ring resonator modulator and forming a self-correcting feedback loop to return the resonant wavelength to a target wavelength.
  12. In paragraph 1, The above intelligent bandwidth management unit is, If the electro-optic conversion efficiency of the above silicon photonics engine drops below a predetermined efficiency threshold due to thermal increase, data streams received from multiple CXL ports are dynamically channel-merged into a number of channels smaller than the number of WDM channels to reduce the signal power per channel, and A CXL-optical integrated controller chipset that redistributes the logical bandwidth of each CXL port in response to the above merging.
  13. In paragraph 6, The above intelligent bandwidth management unit is, A CXL-optical integrated controller chipset that applies an isolation policy to maintain security domain boundaries so that, when two or more logical devices belonging to different security domains among the above MLD logical devices share the same WDM channel, the bandwidth reduction of one logical device is not reallocated to a logical device in another security domain during column-based bandwidth adjustment.

Description

Single-Chip Optical Communication Controller Integrating a CXL Port-Based Silicon Photonics Engine and a Thermal Feedback-Based Intelligent Bandwidth Management System The present invention relates to high-speed memory and device interconnection technology, and more specifically, to a controller chipset that integrates a plurality of ports supporting the Compute Express Link (CXL) protocol, a Silicon Photonics engine using Wavelength Division Multiplexing (WDM), and an intelligent bandwidth management unit that adjusts the data transmission bandwidth of each CXL port in real time by utilizing heat generated during the optical conversion process as a feedback variable, on a single silicon substrate. As workloads such as artificial intelligence inference and learning, high-performance computing (HPC), and large-scale data centers grow rapidly, the speed and capacity of data exchange between processors, memory, and accelerators are emerging as critical bottlenecks in system performance. Conventional DDR-based parallel interfaces have limitations in bandwidth expansion due to constraints on package area and power consumption resulting from the increase in pin count, while high latency overhead has been cited as a problem for PCIe-based serial interfaces. Against this backdrop, the Compute Express Link (CXL) standard emerged. CXL is an open interconnect standard that shares the physical layer of PCIe and provides cache coherency and memory semantics. It enables low-latency, high-bandwidth communication between the CPU and accelerators/memory expanders through three subprotocols: CXL.io, CXL.cache, and CXL.memory. Notably, since CXL 2.0, support for Multi-Logical Device (MLD) mode has enabled a memory pooling architecture where multiple tenants share a single memory pool. However, the electrical signal-based interface defined by the CXL standard carries inherent problems, such as severe signal attenuation at distances exceeding tens of centimeters and a sharp increase in power consumption at lane speeds of tens of Gbps or higher. Silicon photonics-based optical interconnect technology is attracting attention as an approach to address these issues. By utilizing mature CMOS processes to integrate optical components—such as optical waveguides, ring resonator modulators, and germanium photodetectors—on silicon substrates, silicon photonics can achieve bandwidth densities tens of times greater than those of electrical signals and low energy consumption per bit. In particular, the adoption of WDM allows for the simultaneous transmission of multiple wavelength channels through a single optical fiber, enabling the expansion of total transmission capacity to over several Tbps while minimizing the number of physical optical fibers. However, silicon photonic devices, particularly ring resonator modulators used in WDM, have a high thermo-optic coefficient of silicon, reaching approximately 1.84 × 10⁻⁴ /K, causing the resonant wavelength to drift at a rate of tens of pm/°C due to local temperature changes. Since this leads directly to cross-talk and signal quality degradation in WDM systems, very precise temperature control of the ring resonator modulator is essential for maintaining stable optical communication. In conventional technology, these thermal issues have been approached primarily from a hardware perspective. For example, methods such as active wavelength locking using microheaters adjacent to ring resonator modulators, attaching thermoelectric coolers (TECs) to the outside of the package, or applying liquid cooling have been proposed. However, these methods fail to overcome the fundamental limitation that the capacity of cooling hardware is finite. Furthermore, particularly when modulation power increases rapidly during traffic bursts, the cooling device reaches saturation, leading to a breakdown in the wavelength stability of the WDM channel. Furthermore, when the CXL controller and silicon photonics engine are implemented as separate chips or packages, the electrical interface between them involves additional signal processing steps, leading to increased latency, the generation of additional heat in the electrical signal path between the two chips, and a decrease in system integration density. In addition, conventional systems lack a feedback path between the transmission bandwidth of the CXL port (the upper protocol layer) and the thermal state of the optical engine (the lower physical layer), resulting in a structural problem where the CXL port continues to transmit data at maximum bandwidth even when the optical engine is in a thermally unstable state. Therefore, there is a need for a cross-layer thermal-bandwidth coupled control architecture that integrates the CXL controller and the silicon photonics WDM engine into a single chip, detects the heat generated during the optical conversion process in real time, and directly feeds it back to the bandwidth control of the upper-level CXL port. FIG. 1 is an overal