KR-20260068072-A - Rear bidirectional interconnection

Abstract

Techniques for a semiconductor structure are disclosed. In one embodiment, the semiconductor structure comprises a gate stack including a first gate structure and a second gate structure offset in a first direction. The semiconductor structure comprises a first source/drain (S/D) structure adjacent to the first gate structure, a second S/D structure adjacent to the second gate structure, a first back-side conductive structure in contact with the first S/D structure, and a second back-side conductive structure in contact with the second S/D structure. The semiconductor structure comprises a third back-side conductive structure disposed in a rear portion of the semiconductor structure opposite to the front portion of the semiconductor structure, extending along a second direction and in contact with the first back-side conductive structure and the second back-side conductive structure.

Inventors

• 선, 얀
• 샤르마, 디팍
• 나라시마, 슈리쉬

Assignees

• 퀄컴 인코포레이티드

Dates

Publication Date

20260513

Application Date

20240822

Priority Date

20230918

Claims (20)

1. As a semiconductor structure, A gate stack extending along a first direction in a front portion of the semiconductor structure - the gate stack includes a first gate structure and a second gate structure offset from each other in the first direction -; A first source/drain (S/D) structure adjacent to the first gate structure; A second S/D structure adjacent to the second gate structure - the second S/D structure is offset in a second direction from the first S/D structure -; A first rear conductive structure in contact with the first S/D structure and disposed at least partially in the rear portion of the semiconductor structure opposite to the front portion; A second rear conductive structure in contact with the second S/D structure and disposed at least partially in the rear portion of the semiconductor structure; and A semiconductor structure comprising a third rear conductive structure disposed in a rear portion of the semiconductor structure, wherein the third rear conductive structure extends along the second direction and contacts the first rear conductive structure and the second rear conductive structure.
2. In paragraph 1, The first rear conductive structure and the second rear conductive structure are disposed within a first rear metallized layer below the first S/D structure and the second S/D structure, and The above third rear conductive structure is a semiconductor structure disposed within a second rear metallization layer below the first rear metallization layer.
3. In paragraph 2, A fourth rear conductive structure within the second rear metallized layer; and A semiconductor structure further comprising a metallized structure disposed within a third rear metallized layer below the second rear metallized layer, wherein the fourth rear conductive structure connects the metallized structure in the first rear metallized layer to another rear conductive structure.
4. In paragraph 1, The first rear conductive structure and the second rear conductive structure are disposed within a first rear metallized layer below the first S/D structure and the second S/D structure, and The above third rear conductive structure is a semiconductor structure disposed within the lower portion of the above first rear metallized layer.
5. In paragraph 4, A fourth rear conductive structure within a second rear metallization layer below the first rear metallization layer; and A semiconductor structure further comprising a metallized structure disposed within a third rear metallized layer below the second rear metallized layer, wherein the fourth rear conductive structure connects the metallized structure in the first rear metallized layer to another rear conductive structure.
6. In paragraph 1, The dielectric structure is further included below the connection portion of the gate stack between the first gate structure and the second gate structure, and Here, A semiconductor structure wherein the third rear conductive structure is disposed at least partially below the connection portion of the gate stack, and the dielectric structure is configured to electrically isolate the third rear conductive structure from the bottom gate electrode portion of the connection portion of the gate stack.
7. In paragraph 6, The above dielectric structure is a semiconductor structure that contacts the lower gate electrode portion of the connection portion of the gate stack.
8. In Paragraph 7, A semiconductor structure in which at least a portion of the third rear conductive structure is positioned on the lower surface of the gate stack and extends along the internal spacer of the connection portion of the gate stack.
9. In paragraph 6, A semiconductor structure in which the entire third rear conductive structure is located below the connection portion of the gate stack.
10. In paragraph 6, The above dielectric structure is a semiconductor structure comprising an etching stop layer below the connection portion of the gate stack.
11. As a method for manufacturing a semiconductor structure, A step of forming a gate stack extending along a first direction in a front portion of the semiconductor structure above - the gate stack includes a first gate structure and a second gate structure, wherein the second gate structure is offset from the first gate structure in the first direction, a first S/D structure is disposed adjacent to the first gate structure, a second S/D structure is disposed adjacent to the second gate structure, and the first S/D structure and the second S/D structure are offset from each other in a second direction -; A step of forming a first rear conductive structure that is in contact with the first S/D structure and is at least partially disposed in the rear portion of the semiconductor structure opposite to the front portion; A step of forming a second rear conductive structure that contacts the second S/D structure and is at least partially disposed in the rear portion of the semiconductor structure; and A method comprising the step of forming a third rear conductive structure disposed in a rear portion of the semiconductor structure, wherein the third rear conductive structure extends along the second direction and contacts the first rear conductive structure and the second rear conductive structure.
12. In Paragraph 11, The first rear conductive structure and the second rear conductive structure are formed within a first rear metallized layer below the first S/D structure and the second S/D structure, and A method in which the third rear conductive structure is formed within the second rear metallization layer below the first rear metallization layer.
13. In Paragraph 12, A step of forming a fourth rear conductive structure within the second rear metallized layer; and A method further comprising the step of forming a metallized structure disposed within a third rear metallized layer below the second rear metallized layer, wherein the fourth rear conductive structure connects the metallized structure in the first rear metallized layer to another rear conductive structure.
14. In Paragraph 11, The first rear conductive structure and the second rear conductive structure are formed within a first rear metallized layer below the first S/D structure and the second S/D structure, and A method in which the third rear conductive structure is formed within the lower portion of the first rear metallized layer.
15. In Paragraph 14, A step of forming a fourth rear conductive structure within a second rear metallization layer below the first rear metallization layer; and A method further comprising the step of forming a metallized structure within a third rear metallized layer below the second rear metallized layer, wherein the fourth rear conductive structure connects the metallized structure in the first rear metallized layer to another rear conductive structure.
16. In Paragraph 11, The method further includes the step of forming a dielectric structure below the connection portion of the gate stack between the first gate structure and the second gate structure, and Here, A method in which the third rear conductive structure is formed at least partially below the connection portion of the gate stack, and the dielectric structure is configured to electrically isolate the third rear conductive structure from the bottom gate electrode portion of the connection portion of the gate stack.
17. In paragraph 16, the step of forming the above-mentioned genome structure is, A step of removing a portion of the gate dielectric portion of the connection portion of the gate stack to expose the lower gate electrode portion of the connection portion of the gate stack; and A method comprising the step of performing a region-selective deposition process to form the above-mentioned genome structure.
18. In claim 17, the step of forming the third rear conductive structure is, The method includes the step of defining an opening by removing a portion of the front interlayer dielectric layer adjacent to the internal spacer of the connection portion of the gate stack, A method in which the third rear conductive structure is formed in the opening such that at least a portion of the third rear conductive structure is above the lower surface of the gate stack and extends along the internal spacer of the connection portion of the gate stack.
19. In Paragraph 17, A method in which the entire third rear conductive structure is located below the connection portion of the gate laminate.
20. In Paragraph 16, A method further comprising the step of forming an etching stop layer as a dielectric structure below a connection portion of the gate stack.

Description

Rear bidirectional interconnection The present disclosure generally relates to a semiconductor structure of an integrated circuit device, and more specifically, to a semiconductor structure having backside bidirectional interconnects. Integrated circuit (IC) technology has made significant progress in enhancing computing capabilities through the miniaturization of electrical components. IC devices can be implemented in the form of an IC chip in which a set of circuits is integrated, comprising multiple active and passive components (e.g., transistors, diodes, capacitors, inductors, and/or resistors) and layers of contacts and interconnects on the active and passive components. In some embodiments, the contacts and interconnects of the IC device are formed on the active and passive components from the front side of the IC device. As the sizes of IC devices and the components formed thereon become smaller, the available area for forming the contacts and interconnects also becomes smaller. As such, the routing complexity of the contacts and interconnects and/or parasitic resistance and capacitance may increase, and consequently, the manufacturing cost or performance of the IC device may be negatively affected. Therefore, to further reduce routing complexity and/or reduce parasitic resistance and capacitance, improved structures or manufacturing methods for contacts and interconnects are required. The following presents a simplified summary relating to one or more embodiments disclosed herein. Accordingly, the following summary should not be construed as a comprehensive overview relating to all embodiments considered, nor should it be construed as identifying key or decisive elements relating to all embodiments considered, or describing categories associated with any particular embodiment. Accordingly, the following summary is intended solely to present specific concepts relating to one or more embodiments relating to the mechanisms disclosed herein, in a simplified form preceding the detailed description provided below. In one embodiment, the semiconductor structure comprises: a gate stack extending along a first direction in a front portion of the semiconductor structure—the gate stack comprises a first gate structure and a second gate structure offset from each other in a first direction—; a first source/drain (S/D) structure adjacent to the first gate structure; a second S/D structure adjacent to the second gate structure—the second S/D structure is offset from the first S/D structure in a second direction—; a first rear conductive structure in contact with the first S/D structure and disposed at least partially in a rear portion of the semiconductor structure opposite to the front portion; a second rear conductive structure in contact with the second S/D structure and disposed at least partially in a rear portion of the semiconductor structure; and a third rear conductive structure disposed in a rear portion of the semiconductor structure—the third rear conductive structure extends along a second direction and contacts the first rear conductive structure and the second rear conductive structure. In one embodiment, a method for manufacturing a semiconductor structure comprises: forming a gate stack extending along a first direction in a front portion of the semiconductor structure—the gate stack includes a first gate structure and a second gate structure, wherein the second gate structure is offset from the first gate structure in a first direction, a first S/D structure is disposed adjacent to the first gate structure, a second S/D structure is disposed adjacent to the second gate structure, and the first S/D structure and the second S/D structure are offset from each other in a second direction—; forming a first rear conductive structure in contact with the first S/D structure and at least partially disposed in a rear portion of the semiconductor structure opposite to the front portion; forming a second rear conductive structure in contact with the second S/D structure and at least partially disposed in a rear portion of the semiconductor structure; and forming a third rear conductive structure disposed in a rear portion of the semiconductor structure—the third rear conductive structure extends along a second direction and is in contact with the first rear conductive structure and the second rear conductive structure. In one embodiment, the electronic device comprises an integrated circuit device including a semiconductor structure, wherein the semiconductor structure comprises: a gate stack extending along a first direction in a front portion of the semiconductor structure—the gate stack comprises a first gate structure and a second gate structure offset from each other in a first direction—; a first source/drain (S/D) structure adjacent to the first gate structure; a second S/D structure adjacent to the second gate structure—the second S/D structure is offset from the first S/D structure in a second dir