KR-20260068073-A - Self-aligned rear interconnects

Abstract

Techniques for a semiconductor structure are disclosed. In one embodiment, the semiconductor structure comprises: a gate stack extending along a first direction in a front portion of the semiconductor structure and including a first gate structure; a first channel structure disposed through the first gate structure and extending along a second direction; a first source/drain (S/D) structure adjacent to the first gate structure and electrically coupled to the first channel structure; a back dielectric layer disposed in a rear portion of the semiconductor structure opposite to the front portion; and a back conductive structure in contact with the first S/D structure and disposed at least partially in the rear portion of the semiconductor structure and through the back dielectric layer. The back conductive structure has a length in a first direction greater than the width in a first direction of the first channel structure.

Inventors

• 선, 얀
• 나라시마, 슈리쉬

Assignees

• 퀄컴 인코포레이티드

Dates

Publication Date

20260513

Application Date

20240823

Priority Date

20230918

Claims (20)

1. As a semiconductor structure, A gate stack that extends along a first direction in the front portion of the semiconductor structure and includes a first gate structure; A first channel structure disposed through the first gate structure and extending along a second direction from a first surface of the first gate structure to a second surface of the first gate structure; A first source/drain (S/D) structure adjacent to the first gate structure and electrically coupled to the first channel structure; A rear dielectric layer disposed in the rear portion of the semiconductor structure opposite to the front portion; and It includes a rear conductive structure that is in contact with the first S/D structure and is disposed at least partially in the rear portion of the semiconductor structure and through the rear dielectric layer, and A semiconductor structure having a rear conductive structure that extends along the first direction and has a length in the first direction greater than the width in the first direction of the first channel structure.
2. In paragraph 1, A second channel structure disposed through a second gate structure included in the gate stack and extending along the second direction from a third face of the second gate structure to a fourth face of the second gate structure - the second gate structure is offset from the first gate structure in the first direction -; and It further includes a second S/D structure adjacent to the second gate structure and electrically coupled to the second channel structure, A semiconductor structure in which the first S/D structure has a first doping type, and the second S/D structure has a second doping type different from the first doping type.
3. In paragraph 2, The above-mentioned rear conductive structure is a semiconductor structure that extends along the first direction from at least the first S/D structure to an intermediate point between the first S/D structure and the second S/D structure.
4. In paragraph 3, The above-mentioned rear conductive structure is a semiconductor structure that extends along the first direction from the first S/D structure to the second S/D structure and contacts the second S/D structure.
5. In paragraph 1, The first channel structure comprises one or more channel members, and The above-mentioned first gate structure is, Gate electrode structure, and A semiconductor structure comprising one or more gate dielectric structures between the gate electrode structure and each of the one or more channel members.
6. In paragraph 5, A semiconductor structure comprising one or more channel members, each comprising a plurality of nanowires or nanosheets.
7. In paragraph 1, A semiconductor structure in which the upper portion of the above rear conductive structure contacts the lower inner spacer of the first gate structure and the lower inner spacer of another gate structure offset from the first gate structure in the second direction.
8. In Paragraph 7, A semiconductor structure in which the first width in the second direction of the upper part of the rear conductive structure is greater than the second width in the second direction of the lower part of the rear conductive structure.
9. In paragraph 1, It further comprises a metallized structure disposed in a rear portion of the semiconductor structure, located below the rear conductive structure through a rear via and coupled thereto, and The above-mentioned rear via is a semiconductor structure that is offset from the first channel structure in the first direction and does not overlap with it.
10. In paragraph 1, The above-mentioned rear conductive structure is a semiconductor structure comprising tungsten, cobalt, molybdenum, ruthenium, or a combination thereof.
11. As a method for manufacturing a semiconductor structure, Step of forming a first channel structure; A step of forming a first source/drain (S/D) structure electrically coupled to the first channel structure; A step of forming a first gate structure included in a gate stack extending along a first direction in a front portion of the semiconductor structure - the first channel structure is disposed through the first gate structure and extends along a second direction from a first surface of the first gate structure to a second surface of the first gate structure, and the first S/D structure is adjacent to the first gate structure -; A step of forming a rear dielectric layer on the rear portion of the semiconductor structure opposite to the front portion; A step of removing a sacrificial structure within the rear dielectric layer and removing a portion of the epitaxial stop layer below the first S/D structure to define an opening; and The step of forming a rear conductive structure based on the above opening—the rear conductive structure is in contact with the first S/D structure and is disposed at least partially in the rear portion of the semiconductor structure and through the rear dielectric layer—including, A method in which the rear conductive structure extends along the first direction and has a length in the first direction greater than the width in the first direction of the first channel structure.
12. In Paragraph 11, Step of forming a second channel structure; A step of forming a second S/D structure electrically coupled to the second channel structure; and The method further comprises the step of forming a second gate structure included in the gate stack in a front portion of the semiconductor structure—the second gate structure is offset in the first direction from the first gate structure, the second channel structure is disposed through the second gate structure and extends along the second direction from the third surface of the second gate structure to the fourth surface of the second gate structure, and the second S/D structure is adjacent to the second gate structure. A method in which the first S/D structure has a first doping type, and the second S/D structure has a second doping type different from the first doping type.
13. In Paragraph 12, A method in which the above opening is limited such that the rear conductive structure formed based on the above opening extends along the first direction from at least the first S/D structure to an intermediate point between the first S/D structure and the second S/D structure.
14. In Paragraph 13, The above opening is limited so that the rear conductive structure formed based on the above opening extends along the first direction from the first S/D structure to the second S/D structure, and A method in which the above rear conductive structure is formed to be in contact with the above second S/D structure.
15. In Paragraph 11, The first channel structure comprises one or more channel members, and The step of forming the first gate structure is, A step of forming one or more gate dielectric structures on each of the above one or more channel members; and A method comprising the step of forming a gate electrode structure—wherein one or more gate dielectric structures are located between the gate electrode structure and each of the one or more channel members.
16. In paragraph 15, A method in which one or more channel members comprise a plurality of nanowires or nanosheets.
17. In Paragraph 11, A method in which the upper portion of the rear conductive structure contacts the lower inner spacer of the first gate structure and the lower inner spacer of another gate structure offset from the first gate structure in the second direction.
18. In Paragraph 17, A method in which the first width in the second direction of the upper part of the rear conductive structure is greater than the second width in the second direction of the lower part of the rear conductive structure.
19. In Paragraph 11, The method further includes the step of forming a metallized structure in a rear portion of the semiconductor structure and in a contact area of the rear conductive structure, below the rear conductive structure and in contact with it. A method in which the contact area of the above rear conductive structure is offset from the first channel structure in the first direction and does not overlap with it.
20. In Paragraph 11, The above-mentioned rear conductive structure comprises tungsten, cobalt, molybdenum, ruthenium, or a combination thereof.

Description

Self-aligned rear interconnects The present disclosure generally relates to a semiconductor structure of an integrated circuit device, and more specifically, to a semiconductor structure having self-aligned back interconnects. Integrated circuit (IC) technology has made significant progress in enhancing computing capabilities through the miniaturization of electrical components. IC devices can be implemented in the form of an IC chip in which a set of circuits is integrated, comprising multiple active and passive components (e.g., transistors, diodes, capacitors, inductors, and/or resistors) and layers of contacts and interconnects on the active and passive components. In some embodiments, the contacts and interconnects of the IC device are formed on the active and passive components from the front side of the IC device. As the sizes of IC devices and the components formed thereon become smaller, the available area for forming the contacts and interconnects also becomes smaller. As such, the routing complexity of the contacts and interconnects and/or parasitic resistance and capacitance may increase, and consequently, the manufacturing cost or performance of the IC device may be negatively affected. Therefore, to further reduce routing complexity and/or reduce parasitic resistance and capacitance, improved structures or manufacturing methods for contacts and interconnects are required. The following presents a simplified summary relating to one or more embodiments disclosed herein. Accordingly, the following summary should not be construed as a comprehensive overview relating to all embodiments considered, nor should it be construed as identifying key or decisive elements relating to all embodiments considered, or describing categories associated with any particular embodiment. Accordingly, the following summary is intended solely to present specific concepts relating to one or more embodiments relating to the mechanisms disclosed herein, in a simplified form preceding the detailed description provided below. In one embodiment, the semiconductor structure comprises: a gate stack including a first gate structure extending along a first direction in a front portion of the semiconductor structure; a first channel structure disposed through the first gate structure and extending along a second direction from a first surface of the first gate structure to a second surface of the first gate structure; a first source/drain (S/D) structure adjacent to the first gate structure and electrically coupled to the first channel structure; a back dielectric layer disposed in a rear portion of the semiconductor structure opposite to the front portion; and a back conductive structure in contact with the first S/D structure and disposed at least partially in the rear portion of the semiconductor structure and through the back dielectric layer, wherein the back conductive structure extends along a first direction and has a length in a first direction greater than the width in a first direction of the first channel structure. In one embodiment, a method for manufacturing a semiconductor structure comprises: forming a first channel structure; forming a first source/drain (S/D) structure electrically coupled to the first channel structure; forming a first gate structure included in a gate stack extending along a first direction in a front portion of the semiconductor structure, wherein the first channel structure is disposed through the first gate structure and extends along a second direction from a first surface of the first gate structure to a second surface of the first gate structure, and the first S/D structure is adjacent to the first gate structure; forming a back dielectric layer in a rear portion of the semiconductor structure opposite to the front portion; and removing a sacrificial structure in the back dielectric layer and removing a portion of an epitaxial stop layer under the first S/D structure to define an opening. The method comprises the step of forming a rear conductive structure based on an opening, wherein the rear conductive structure is in contact with the first S/D structure and is disposed at least partially through the rear portion of the semiconductor structure and through the rear dielectric layer, and the rear conductive structure extends along a first direction and has a length in the first direction greater than the width in the first direction of the first channel structure. In one embodiment, the electronic device comprises an integrated circuit device including a semiconductor structure, wherein the semiconductor structure comprises: a gate stack including a first gate structure extending along a first direction in a front portion of the semiconductor structure; a first channel structure disposed through the first gate structure and extending along a second direction from a first surface of the first gate structure to a second surface of the first gate structure; a first source/drain (S/D) struc