KR-20260068074-A - A package comprising a substrate having a cavity and an integrated device located in the cavity of the substrate.

Abstract

The package comprises: a first substrate; a first integrated device coupled to the first substrate through at least a first plurality of solder interconnects; a second substrate coupled to the first substrate through at least a second plurality of solder interconnects, wherein the second substrate includes a cavity; and an encapsulation layer located between at least the first substrate and the second substrate, wherein the encapsulation layer is coupled to the first substrate, the second substrate and the first integrated device.

Inventors

• 연 재현
• 팡 쿤
• 황 수형
• 이 상재
• 쿠마르 라지네쉬
• 알드레테 마누엘
• 왕 지제
• 김 성호

Assignees

• 퀄컴 인코포레이티드

Dates

Publication Date

20260513

Application Date

20240906

Priority Date

20230920

Claims (20)

1. As a package, First substrate; A first integrated device coupled to the first substrate through at least a first plurality of solder interconnects; A second substrate coupled to the first substrate through at least a second plurality of solder interconnects, wherein the second substrate comprises a cavity; and A package comprising an encapsulation layer positioned at least between the first substrate and the second substrate, wherein the encapsulation layer is coupled to the first substrate, the second substrate and the first integrated device.
2. In claim 1, the package, wherein the encapsulation layer is located in at least a part of the cavity of the second substrate.
3. In claim 1, the encapsulation layer encapsulates at least a portion of the first integrated device, a package.
4. In paragraph 1, The second substrate above includes a solder resist layer, and A portion of the above encapsulation layer is positioned on the above solder resist layer, a package.
5. A package according to claim 1, further comprising a second integrated device coupled to the first integrated device through at least a third plurality of solder interconnects.
6. In claim 5, the package, wherein the front surface of the second integrated device faces the direction of the rear surface of the first integrated device.
7. In claim 5, the encapsulation layer encapsulates at least a portion of the first integrated device and at least a portion of the second integrated device, in a package.
8. In claim 5, the first integrated device and/or the second integrated device are at least partially located in the cavity of the second substrate, in a package.
9. In paragraph 5, A thermal interface material coupled to the second integrated device; and A package further comprising a heat sink coupled to the second integrated device through the thermal interface material.
10. In claim 9, the first integrated device, the second integrated device and/or the heat sink are at least partially located in the cavity of the second substrate, in a package.
11. In claim 9, the heat sink is coupled to the rear surface of the second integrated device through the thermal interface material, in a package.
12. A package according to claim 9, further comprising a third integrated device coupled to the second substrate through a fourth plurality of solder interconnects.
13. A package according to claim 5, further comprising a third integrated device coupled to the second substrate through a fourth plurality of solder interconnects.
14. A package according to claim 1, further comprising a second integrated device coupled to the second substrate through a third plurality of solder interconnects.
15. In claim 1, the second substrate comprises a package including an interposer comprising a plurality of interposer interconnects.
16. In paragraph 1, The first integrated device above includes a die substrate, and The above die substrate has a thickness in the range of approximately 32-792 micrometers, and The first integrated device is a package having a thickness in the range of about 40 to 800 micrometers.
17. In Paragraph 16, The first substrate has a thickness in the range of about 100-300 micrometers, and The second substrate has a thickness in the range of about 50 to 150 micrometers, and A package having a thickness of approximately 100-300 micrometers in the range of the encapsulation layer.
18. In claim 1, the die substrate from the first integrated device comprises a plurality of through-substrate vias, forming a package.
19. In claim 1, the die substrate from the first integrated device comprises a plurality of dummy through-substrate vias, forming a package.
20. The package according to claim 1, wherein the package is implemented in a device selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smartphone, a personal portable information terminal, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, and an in-vehicle device.

Description

A package comprising a substrate having a cavity and an integrated device located in the cavity of the substrate. Cross-reference regarding related applications This application claims priority and interest in U.S. Regular Application No. 18/471,069 filed with the U.S. Patent and Trademark Office on September 20, 2023, the whole of which is incorporated herein by reference as fully described below and for all applicable purposes. Technology field Various features relate to packages having substrates and integrated devices. A package may include a substrate and integrated devices. These components are coupled together to provide a package capable of performing various electrical functions. These components can generate a significant amount of heat that must be efficiently dissipated, as excessive heat can negatively impact the performance of the integrated device and/or package. There is a continuous need for improved heat dissipation in packages, the provision of higher-performance packages, and the reduction of the overall package size. Various features relate to packages having substrates and integrated devices. One example includes a package, wherein the package comprises: a first substrate; a first integrated device coupled to the first substrate through at least a first plurality of solder interconnects; a second substrate coupled to the first substrate through at least a second plurality of solder interconnects, wherein the second substrate comprises a cavity; and an encapsulation layer positioned between at least the first substrate and the second substrate, wherein the encapsulation layer is coupled to the first substrate, the second substrate and the first integrated device. Various features, attributes, and advantages may become apparent from the detailed description below when taken together with the drawings, and in the drawings, the same reference numerals are identified correspondingly throughout. FIG. 1 illustrates an exemplary cross-sectional profile view of a package comprising a substrate having a cavity and an integrated device located in the cavity of the substrate. FIG. 2 illustrates an exemplary cross-sectional profile view of an integrated device. FIG. 3 illustrates an exemplary planar view of a package including a substrate having a cavity and an integrated device located in the cavity of the substrate. FIG. 4 illustrates an exemplary cross-sectional profile view of a package including a substrate having a cavity and an integrated device located in the cavity of the substrate. FIG. 5 illustrates an exemplary cross-sectional profile view of a package including a substrate having a cavity and an integrated device located in the cavity of the substrate. FIG. 6 illustrates an exemplary cross-sectional profile view of a package including a substrate having a cavity and an integrated device located in the cavity of the substrate. FIGS. 7a through 7e illustrate an exemplary sequence for manufacturing a package comprising a substrate having a cavity and an integrated device located in the cavity of the substrate. FIG. 8 illustrates an exemplary flowchart of a method for manufacturing a package comprising a substrate having a cavity and an integrated device located in the cavity of the substrate. FIG. 9 illustrates an exemplary sequence for manufacturing a substrate having a cavity, wherein the substrate may include an interposer. FIGS. 10a and FIGS. 10b illustrate an exemplary sequence for manufacturing a substrate. FIG. 11 illustrates various electronic devices capable of integrating the die, electronic circuit, integrated device, integrated passive device (IPD), passive component, package, and/or device package described herein. In the following description, specific details are provided to provide a complete understanding of the various embodiments of the invention. However, it will be understood by those skilled in the art that the embodiments may be practiced without these specific details. For example, circuits may be illustrated in block diagrams to avoid obscuring the embodiments with unnecessary detail. In other examples, well-known circuits, structures, and techniques may not be illustrated in detail to avoid obscuring the embodiments of the present disclosure. The present disclosure describes a package, wherein the package comprises: a first substrate; a first integrated device coupled to the first substrate through at least a first plurality of solder interconnects; a second substrate coupled to the first substrate through at least a second plurality of solder interconnects, wherein the second substrate comprises a cavity; and an encapsulation layer positioned between at least the first substrate and the second substrate, wherein the encapsulation layer is coupled to the first substrate, the second substrate, and the first integrated device. As further described below, the cavity in the second substrate allows an integrated device having a thicker die substrate to be positioned i