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US-12618158-B2 - Semiconductor device manufacturing method

US12618158B2US 12618158 B2US12618158 B2US 12618158B2US-12618158-B2

Abstract

Provided is a manufacturing method of a semiconductor device, comprising: performing a zincate treatment on a first metal layer provided above a semiconductor substrate with a zincate solution; forming a nickel-plated layer above the first metal layer; and forming a gold-plated layer above the nickel-plated layer, wherein in the performing the zincate treatment, a flow rate of the zincate solution supplied to a bath for performing the zincate treatment is 16 L/min or more and 20 L/min or less.

Inventors

  • Yuya Takahashi
  • Shunsuke Tanaka

Assignees

  • FUJI ELECTRIC CO., LTD.

Dates

Publication Date
20260505
Application Date
20230721
Priority Date
20220927

Claims (20)

  1. 1 . A manufacturing method of a semiconductor device, comprising: performing a zincate treatment on a first metal layer provided above a semiconductor substrate with a zincate solution; forming a nickel-plated layer above the first metal layer; and forming a gold-plated layer above the nickel-plated layer, wherein in the performing the zincate treatment, a flow rate of the zincate solution supplied to a bath for performing the zincate treatment is 16 L/min or more and 20 L/min or less.
  2. 2 . The manufacturing method of the semiconductor device according to claim 1 , wherein the zincate solution includes all of sodium hydroxide, oxycarboxylic acid, sodium sulfate, zinc oxide, and iron.
  3. 3 . The manufacturing method of the semiconductor device according to claim 2 , wherein a zinc concentration in the zincate solution is 2.0 g/L or more and 3.0 g/L or less.
  4. 4 . The manufacturing method of the semiconductor device according to claim 3 , wherein an iron concentration in the zincate solution is 0.25 g/L or more and 0.35 g/L or less.
  5. 5 . The manufacturing method of the semiconductor device according to claim 1 , wherein a wettability of solder when the solder is applied on the gold-plated layer is 80% or more and 90% or less.
  6. 6 . The manufacturing method of the semiconductor device according to claim 5 , wherein the solder includes all of tin, silver, copper, nickel, and germanium.
  7. 7 . The manufacturing method of the semiconductor device according to claim 1 , wherein in the forming the nickel-plated layer, a flow rate of a nickel plating solution supplied to a bath for performing a nickel plating treatment on the semiconductor substrate is 16 L/min or more and 20 L/min or less.
  8. 8 . The manufacturing method of the semiconductor device according to claim 7 , wherein the zincate solution includes all of sodium hydroxide, oxycarboxylic acid, sodium sulfate, zinc oxide, and iron.
  9. 9 . The manufacturing method of the semiconductor device according to claim 8 , wherein a zinc concentration in the zincate solution is 2.0 g/L or more and 3.0 g/L or less.
  10. 10 . The manufacturing method of the semiconductor device according to claim 9 , wherein an iron concentration in the zincate solution is 0.25 g/L or more and 0.35 g/L or less.
  11. 11 . The manufacturing method of the semiconductor device according to claim 7 , wherein a wettability of solder when the solder is applied on the gold-plated layer is 80% or more and 90% or less.
  12. 12 . The manufacturing method of the semiconductor device according to claim 7 , wherein a nickel concentration in the nickel plating solution is 4.5 g/L or more and 4.7 g/L or less.
  13. 13 . The manufacturing method of the semiconductor device according to claim 12 , wherein the zincate solution includes all of sodium hydroxide, oxycarboxylic acid, sodium sulfate, zinc oxide, and iron.
  14. 14 . The manufacturing method of the semiconductor device according to claim 13 , wherein a zinc concentration in the zincate solution is 2.0 g/L or more and 3.0 g/L or less.
  15. 15 . The manufacturing method of the semiconductor device according to claim 14 , wherein an iron concentration in the zincate solution is 0.25 g/L or more and 0.35 g/L or less.
  16. 16 . The manufacturing method of the semiconductor device according to claim 12 , wherein a wettability of solder when the solder is applied on the gold-plated layer is 80% or more and 90% or less.
  17. 17 . The manufacturing method of the semiconductor device according to claim 1 , wherein a film formation rate of the nickel-plated layer is 0.1 μm/min or more and 0.2 μm/min or less.
  18. 18 . The manufacturing method of the semiconductor device according to claim 1 , wherein a film thickness of the gold-plated layer is 0.01 μm or more and 0.1 μm or less.
  19. 19 . The manufacturing method of the semiconductor device according to claim 1 , wherein the first metal layer includes at least either aluminum or an aluminum-silicon alloy.
  20. 20 . The manufacturing method of the semiconductor device according to claim 1 , comprising forming a palladium-plated layer above the nickel-plated layer after the forming the nickel-plated layer above the first metal layer and before the forming the gold-plated layer above the nickel-plated layer.

Description

The contents of the following patent application(s) are incorporated herein by reference: NO. 2022-153807 filed in JP on Sep. 27, 2022 BACKGROUND 1. Technical Field The present invention relates to a manufacturing method of a semiconductor device. 2. Related Art In Patent Document 1, it is described: “the surface of the metal plating is treated with a sealing agent prepared by dissolving at least one kind out of a neopentyl fatty acid ester, a dibasic acid, and an amine salt of dibasic acid, in at least one kind of solvent, such as alcohol-based, chlorine-based, and fluorine-based ones”. PRIOR ART DOCUMENT Patent Document Patent Document 1: Japanese Patent Application Publication No. 2001-237262.Patent Document 2: WO 2021/020064.Patent Document 3: Japanese Patent Application Publication No. 2008-248371.Patent Document 4: WO 2019/163484.Patent Document 5: Japanese Patent Application Publication No. 2020-120133. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 illustrates an example of a cross-sectional view of a semiconductor device 100. FIG. 2 illustrates an example of a manufacturing process of an electrode portion 20. FIG. 3A illustrates an example of a cross-sectional view of a zincate process S102. FIG. 3B illustrates an example of a cross-sectional view of a zincate process of a comparative example. FIG. 4 illustrates an example of a schematic view of the zincate process to a gold plating process of the comparative example. FIG. 5A illustrates an example of a surface picture of the electrode portion 20 after a gold plating process of the practical example. FIG. 5B illustrates an example of a surface picture of an electrode portion after the gold plating process of the comparative example. FIG. 6 illustrates an example of a cross-sectional view of the gold plating process and a dicing process of the comparative example. FIG. 7A illustrates an example of a surface picture when solder is dropped on the electrode portion 20 after the gold plating process of the practical example. FIG. 7B illustrates an example of a surface picture when solder is dropped on the electrode portion after the gold plating process of the comparative example. FIG. 8 shows a variation of the manufacturing process of the electrode portion 20. DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, embodiments of the present invention will be described, but the following embodiments are not for limiting the invention according to the claims. In addition, not all of the combinations of features described in the embodiments are essential to the solution of the invention. In the present specification, one side in a direction parallel to a depth direction of a semiconductor substrate is referred to as “upper”, and the other side is referred to as “lower”. One of two main surfaces of a substrate, a layer, or other members is referred to as an “upper surface”, and the other surface is referred to as a “lower surface”. The “upper”, “lower”, “front”, and “back” directions are not limited to the gravitational direction or the direction of attachment to a substrate or the like at the time of mounting of a semiconductor device. FIG. 1 illustrates an example of a cross-sectional view of a semiconductor device 100. The semiconductor device 100 comprises a semiconductor substrate 10 and an electrode portion 20. The electrode portion 20 includes a first metal layer 22, a nickel-plated layer 24, and a gold-plated layer 26. The semiconductor device 100 may be in wafer form or may be in chip form. By way of example, the semiconductor device 100 may be a reverse conducting IGBT (RC-IGBT). The semiconductor substrate 10 may be a silicon substrate, may be a silicon carbide substrate, or may be a nitride semiconductor substrate, such as a gallium nitride semiconductor substrate, or the like. The electrode portion 20 is provided above the semiconductor substrate 10. The electrode portion 20 may be used to electrically connect the semiconductor device 100 with the outside of the semiconductor device 100. The electrode portion 20 may be electrically connected with the outside of the semiconductor device 100 by a bonding wire. The electrode portion 20 may be electrically connected with a conductive member, such as a lead frame, by using solder. By way of example, the electrode portion 20 may be an emitter electrode provided to an RC-IGBT. By way of another example, the electrode portion 20 may be a collector electrode provided to an RC-IGBT. The first metal layer 22 is provided above the semiconductor substrate 10. The first metal layer 22 may include at least either aluminum or an aluminum-silicon alloy. In the present example, the first metal layer 22 includes an aluminum-silicon alloy. The nickel-plated layer 24 is provided above the first metal layer 22. The nickel-plated layer 24 may contain phosphorous. The phosphorous content in the nickel-plated layer 24 may be 5 mass % or more and 10 mass % or less. Containing phosphorous facilitates the nickel-plated layer 24 to